The current relocation don't work correct, as it doesn't clear the
initial ram (dcache) after relocation. This leads to missing bootargs
during Linux boot. Additionally the current relocation use the sdram
address for the initial ram which introduce a bug in the sdram
initialization.
This patch extend the relocation in order to disable the mmu and to
clear the dcache after the relocation. Additionally it makes the
initial ram address and size configurable and fix the various
CONFIG_SYS_INIT_SP_ADDR definitions in the pxa board config files.
Signed-off-by: Stefan Herbrechtsmeier <sherb...@cit-ec.uni-bielefeld.de>
CC: Marek Vasut <marek.va...@gmail.com>
CC: Prakash Kumar <prak...@embedx.com>
CC: Robert Schwebel <r.schwe...@pengutronix.de>
CC: Cliff Brake <cliff.br...@gmail.com>
CC: Stefano Babic <sba...@denx.de>
---
arch/arm/cpu/pxa/start.S | 38 ++++++++++++++++++++++++++++----------
include/configs/balloon3.h | 7 +++++--
include/configs/cerf250.h | 6 +++++-
include/configs/colibri_pxa270.h | 6 +++++-
include/configs/cradle.h | 6 +++++-
include/configs/csb226.h | 6 +++++-
include/configs/innokom.h | 6 +++++-
include/configs/lubbock.h | 6 +++++-
include/configs/palmld.h | 6 +++++-
include/configs/palmtc.h | 6 +++++-
include/configs/pleb2.h | 6 +++++-
include/configs/pxa255_idp.h | 6 +++++-
include/configs/trizepsiv.h | 6 +++++-
include/configs/vpac270.h | 7 +++++--
include/configs/xaeniax.h | 6 +++++-
include/configs/xm250.h | 6 +++++-
include/configs/zipitz2.h | 6 +++++-
17 files changed, 108 insertions(+), 28 deletions(-)
diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S
index 6191a73..2a2d722 100644
--- a/arch/arm/cpu/pxa/start.S
+++ b/arch/arm/cpu/pxa/start.S
@@ -185,7 +185,7 @@ reset:
/* Flush TLB */
mcr p15, 0, r0, c8, c7, 0
- /* Allocate 4096 bytes of Dcache as RAM */
+ /* Allocate CONFIG_SYS_INIT_RAM_SIZE bytes of Dcache as RAM */
/* Drain pending loads and stores */
mcr p15, 0, r0, c7, c10, 4
@@ -196,9 +196,9 @@ reset:
mcr p15, 0, r0, c9, c2, 0
CPWAIT r0
- /* 128 lines reserved (128 x 32bytes = 4096 bytes total) */
- mov r0, #128
- mov r1, #0xa0000000
+ /* lines to reserve (32bytes per cache line) */
+ ldr r0, =(CONFIG_SYS_INIT_RAM_SIZE >> 5)
+ ldr r1, =(CONFIG_SYS_INIT_RAM_ADDR)
alloc:
mcr p15, 0, r1, c7, c2, 5
/* Drain pending loads and stores */
@@ -316,6 +316,20 @@ clbss_l:str r2, [r0] /* clear
loop... */
add r0, r0, #4
cmp r0, r1
bne clbss_l
+
+disable_mmu:
+ mov r0, #0
+ /* Flush Dcache */
+ mcr p15, 0, r0, c7, c6, 0
+
+ /* Flush dTLB */
+ mcr p15, 0, r0, c8, c6, 0
+
+ /* Disable MMU and DCache */
+ mrc p15, 0, r0, c1, c0, 0
+ bic r0, #0x0005 /* (---- -C-M) */
+ mcr p15, 0, r0, c1, c0, 0
+ CPWAIT r0
#endif /* #ifndef CONFIG_SPL_BUILD */
/*
@@ -589,18 +603,22 @@ reset_endless:
.align 14
.globl mmu_table
mmu_table:
- /* 0x00000000 - 0xa0000000 : 1:1, uncached mapping */
+ /* 0x00000000 -- CONFIG_SYS_INIT_RAM_ADDR */
+ /* 1:1, uncached mapping */
.set __base, 0
- .rept 0xa00
+ .rept CONFIG_SYS_INIT_RAM_ADDR >> 20
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
- /* 0xa0000000 - 0xa0100000 : 1:1, cached mapping */
- .word (0xa00 << 20) | 0x1c1e
+ /* CONFIG_SYS_INIT_RAM_ADDR -- CONFIG_SYS_INIT_RAM_ADDR + 0x100000 */
+ /* 1:1, cached mapping */
+ .word CONFIG_SYS_INIT_RAM_ADDR | 0x1c1e
- .set __base, 0xa01
- .rept 0x1000 - 0xa01
+ /* CONFIG_SYS_INIT_RAM_ADDR + 0x100000 -- 0x100000000 */
+ /* 1:1, uncached mapping */
+ .set __base, (CONFIG_SYS_INIT_RAM_ADDR >> 20) + 1
+ .rept 0x1000 - ((CONFIG_SYS_INIT_RAM_ADDR >> 20) + 1)
.word (__base << 20) | 0xc12
.set __base, __base + 1
.endr
diff --git a/include/configs/balloon3.h b/include/configs/balloon3.h
index b604b52..36cb896 100644
--- a/include/configs/balloon3.h
+++ b/include/configs/balloon3.h
@@ -132,8 +132,11 @@
#define CONFIG_SYS_LOAD_ADDR 0xa1000000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
diff --git a/include/configs/cerf250.h b/include/configs/cerf250.h
index be325e8..1fe34d8 100644
--- a/include/configs/cerf250.h
+++ b/include/configs/cerf250.h
@@ -155,7 +155,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* GPIO settings
diff --git a/include/configs/colibri_pxa270.h b/include/configs/colibri_pxa270.h
index 011731b..ce3432d 100644
--- a/include/configs/colibri_pxa270.h
+++ b/include/configs/colibri_pxa270.h
@@ -167,7 +167,11 @@
#define CONFIG_SYS_LOAD_ADDR (0xa1000000)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
diff --git a/include/configs/cradle.h b/include/configs/cradle.h
index 25be616..2ee875d 100644
--- a/include/configs/cradle.h
+++ b/include/configs/cradle.h
@@ -138,7 +138,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* FLASH and environment organization
diff --git a/include/configs/csb226.h b/include/configs/csb226.h
index 804469b..0fadee0 100644
--- a/include/configs/csb226.h
+++ b/include/configs/csb226.h
@@ -180,7 +180,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
# if 0
/* FIXME: switch to _documented_ registers */
diff --git a/include/configs/innokom.h b/include/configs/innokom.h
index a0a3da1..0a5eba2 100644
--- a/include/configs/innokom.h
+++ b/include/configs/innokom.h
@@ -195,7 +195,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* JFFS2 partitions
diff --git a/include/configs/lubbock.h b/include/configs/lubbock.h
index bbdae3c..fe9f711 100644
--- a/include/configs/lubbock.h
+++ b/include/configs/lubbock.h
@@ -175,7 +175,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
#define FPGA_REGS_BASE_PHYSICAL 0x08000000
diff --git a/include/configs/palmld.h b/include/configs/palmld.h
index 514bcaa..0259b41 100644
--- a/include/configs/palmld.h
+++ b/include/configs/palmld.h
@@ -156,7 +156,11 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
diff --git a/include/configs/palmtc.h b/include/configs/palmtc.h
index bdb5f57..6ef363a 100644
--- a/include/configs/palmtc.h
+++ b/include/configs/palmtc.h
@@ -157,7 +157,11 @@
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
diff --git a/include/configs/pleb2.h b/include/configs/pleb2.h
index 7dd6246..a9b0523 100644
--- a/include/configs/pleb2.h
+++ b/include/configs/pleb2.h
@@ -174,7 +174,11 @@
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* GPIO settings
diff --git a/include/configs/pxa255_idp.h b/include/configs/pxa255_idp.h
index cd95081..77edeb0 100644
--- a/include/configs/pxa255_idp.h
+++ b/include/configs/pxa255_idp.h
@@ -291,7 +291,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* GPIO settings
diff --git a/include/configs/trizepsiv.h b/include/configs/trizepsiv.h
index 6ec9b80..3c38a19 100644
--- a/include/configs/trizepsiv.h
+++ b/include/configs/trizepsiv.h
@@ -213,7 +213,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* GPIO settings
diff --git a/include/configs/vpac270.h b/include/configs/vpac270.h
index 9db4d99..2537704 100644
--- a/include/configs/vpac270.h
+++ b/include/configs/vpac270.h
@@ -181,8 +181,11 @@
#define CONFIG_SYS_LOAD_ADDR PHYS_SDRAM_1
#define CONFIG_SYS_IPL_LOAD_ADDR (0x5c000000)
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR \
- (PHYS_SDRAM_1 + GENERATED_GBL_DATA_SIZE + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
diff --git a/include/configs/xaeniax.h b/include/configs/xaeniax.h
index 8a41416..8275b70 100644
--- a/include/configs/xaeniax.h
+++ b/include/configs/xaeniax.h
@@ -168,7 +168,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* FLASH and environment organization
diff --git a/include/configs/xm250.h b/include/configs/xm250.h
index a35bce3..9254793 100644
--- a/include/configs/xm250.h
+++ b/include/configs/xm250.h
@@ -175,7 +175,11 @@
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* FLASH and environment organization
diff --git a/include/configs/zipitz2.h b/include/configs/zipitz2.h
index ade40b5..e9c2774 100644
--- a/include/configs/zipitz2.h
+++ b/include/configs/zipitz2.h
@@ -177,7 +177,11 @@ unsigned char zipitz2_spi_read(void);
#define CONFIG_SYS_LOAD_ADDR CONFIG_SYS_DRAM_BASE
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
-#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE +
PHYS_SDRAM_1 + 2048)
+#define CONFIG_SYS_INIT_RAM_ADDR 0xc0000000 /* D-Cache */
+#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* 4 kB */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
+ CONFIG_SYS_INIT_RAM_SIZE - \
+ GENERATED_GBL_DATA_SIZE)
/*
* NOR FLASH
--
1.7.0.4
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
