the cache also needs to be invalidated, not just flushed, Since re-enabling it,
can cause inconsistent data without invalidation.
Signed-off-by: Bas van den Berg <b.van.den.berg...@gmail.com>
---
arch/arm/lib/cache.c | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index b545fb7..10eb8c9 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -37,6 +37,8 @@ void __flush_cache(unsigned long start, unsigned long size)
asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory");
/* disable write buffer as well (page 2-22) */
asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0));
+ /* Invalidate dcache as well */
+ asm("mcr p15, 0, %0, c7, c6, 0" : : "r" (0));
#endif
return;
}
--
1.7.0.4
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