On 17 November 2011 16:41, Lukasz Majewski <l.majew...@samsung.com> wrote:
> This patch adds support for Samsung's Exynos4 Nuri reference > board. > > New exynos4_nuri board has been added to boards.cfg > > Signed-off-by: Lukasz Majewski <l.majew...@samsung.com> > Signed-off-by: Kyungmin Park <kyungmin.p...@samsung.com> > Cc: Minkyu Kang <mk7.k...@samsung.com> > --- > Changes for v2: > - MAINTAINERS file updated > - CONFIG_MACH_TYPE added > - hw_revision routine > Changes for v3: > - Entry to MAINTAINERS file added to preserve an alphabetical order > - Redefinition of MACH_TYPE removed from exynos4_nuri.h > - Code cleanup (dead spaces removed) > > ./tools/checkpatch.pl - > total: 0 errors, 0 warnings, 867 lines checked > > NOTE: Ignored message types: COMPLEX_MACRO CONSIDER_KSTRTO MINMAX > MULTISTATEMENT_MACRO_USE_DO_WHILE > --- > MAINTAINERS | 4 + > board/samsung/nuri/Makefile | 45 ++++ > board/samsung/nuri/lowlevel_init.S | 395 > ++++++++++++++++++++++++++++++++++++ > board/samsung/nuri/nuri.c | 201 ++++++++++++++++++ > boards.cfg | 1 + > include/configs/exynos4_nuri.h | 209 +++++++++++++++++++ > 6 files changed, 855 insertions(+), 0 deletions(-) > create mode 100644 board/samsung/nuri/Makefile > create mode 100644 board/samsung/nuri/lowlevel_init.S > create mode 100644 board/samsung/nuri/nuri.c > create mode 100644 include/configs/exynos4_nuri.h > > diff --git a/MAINTAINERS b/MAINTAINERS > index 576fea8..aa1fc15 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -724,6 +724,10 @@ Valentin Longchamp <valentin.longch...@keymile.com> > km_kirkwood ARM926EJS (Kirkwood SoC) > portl2 ARM926EJS (Kirkwood SoC) > > +Łukasz Majewski <l.majew...@samsung.com> > + > + exynos4_nuri ARM ARMV7 (S5PC210 SoC) > + > Nishanth Menon <n...@ti.com> > > omap3_sdp3430 ARM ARMV7 (OMAP3xx SoC) > diff --git a/board/samsung/nuri/Makefile b/board/samsung/nuri/Makefile > new file mode 100644 > index 0000000..27566de > --- /dev/null > +++ b/board/samsung/nuri/Makefile > @@ -0,0 +1,45 @@ > +# > +# Copyright (C) 2010 Samsung Electronics > +# Minkyu Kang <mk7.k...@samsung.com> > +# > +# See file CREDITS for list of people who contributed to this > +# project. > +# > +# This program is free software; you can redistribute it and/or > +# modify it under the terms of the GNU General Public License as > +# published by the Free Software Foundation; either version 2 of > +# the License, or (at your option) any later version. > +# > +# This program is distributed in the hope that it will be useful, > +# but WITHOUT ANY WARRANTY; without even the implied warranty of > +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > +# GNU General Public License for more details. > +# > +# You should have received a copy of the GNU General Public License > +# along with this program; if not, write to the Free Software > +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, > +# MA 02111-1307 USA > +# > + > +include $(TOPDIR)/config.mk > + > +LIB = $(obj)lib$(BOARD).o > + > +COBJS-y := nuri.o > +SOBJS := lowlevel_init.o > + > +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) > +OBJS := $(addprefix $(obj),$(COBJS-y)) > +SOBJS := $(addprefix $(obj),$(SOBJS)) > + > +$(LIB): $(obj).depend $(SOBJS) $(OBJS) > + $(call cmd_link_o_target, $(SOBJS) $(OBJS)) > + > +######################################################################### > + > +# defines $(obj).depend target > +include $(SRCTREE)/rules.mk > + > +sinclude $(obj).depend > + > +######################################################################### > diff --git a/board/samsung/nuri/lowlevel_init.S > b/board/samsung/nuri/lowlevel_init.S > new file mode 100644 > index 0000000..67635bb > --- /dev/null > +++ b/board/samsung/nuri/lowlevel_init.S > @@ -0,0 +1,395 @@ > +/* > + * Lowlevel setup for universal board based on S5PC210 > + * > + * Copyright (C) 2010 Samsung Electronics > + * Kyungmin Park <kyungmin.p...@samsung.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <config.h> > +#include <version.h> > +#include <asm/arch/cpu.h> > +#include <asm/arch/clock.h> > + > +/* > + * Register usages: > + * > + * r5 has zero always > + * r7 has GPIO part1 base 0x11400000 > + * r6 has GPIO part2 base 0x11000000 > + */ > + > + .globl lowlevel_init > +lowlevel_init: > + mov r11, lr > + > + /* r5 has always zero */ > + mov r5, #0 > + > + ldr r7, =S5PC210_GPIO_PART1_BASE > + ldr r6, =S5PC210_GPIO_PART2_BASE > + > + /* System Timer */ > + ldr r0, =S5PC210_SYSTIMER_BASE > + ldr r1, =0x5000 > + str r1, [r0, #0x0] > + ldr r1, =0xffffffff > + str r1, [r0, #0x8] > + ldr r1, =0x49 > + str r1, [r0, #0x4] > + > + /* PMIC manual reset */ > + /* nPOWER: XEINT_23: GPX2[7] */ > + add r0, r6, #0xC40 @ S5PC210_GPIO_X2_OFFSET > + ldr r1, [r0, #0x0] > + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit > + orr r1, r1, #(0x1 << 28) @ Output > + str r1, [r0, #0x0] > + > + ldr r1, [r0, #0x4] > + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit > + str r1, [r0, #0x4] > + > + /* init system clock */ > + bl system_clock_init > + > + /* Disable Watchdog */ > + ldr r0, =S5PC210_WATCHDOG_BASE @0x10060000 > + str r5, [r0] > + > + /* UART */ > + bl uart_asm_init > + > + /* PMU init */ > + bl system_power_init > + > + bl tzpc_init > + > + mov lr, r11 > + mov pc, lr > + nop > + nop > + nop > + > +/* > + * uart_asm_init: Initialize UART's pins > + */ > +uart_asm_init: > + /* > + * setup UART0-UART4 GPIOs (part1) > + * GPA1CON[3] = I2C_3_SCL (3) > + * GPA1CON[2] = I2C_3_SDA (3) > + */ > + mov r0, r7 > + ldr r1, =0x22222222 > + str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET > + ldr r1, =0x00223322 > + str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET > + > + /* UART_SEL GPY4[7] (part2) at S5PC210 */ > + add r0, r6, #0x1A0 @ S5PC210_GPIO_Y4_OFFSET > + ldr r1, [r0, #0x0] > + bic r1, r1, #(0xf << 28) @ 28 = 7 * 4-bit > + orr r1, r1, #(0x1 << 28) > + str r1, [r0, #0x0] > + > + ldr r1, [r0, #0x8] > + bic r1, r1, #(0x3 << 14) @ 14 = 7 * 2-bit > + orr r1, r1, #(0x3 << 14) @ Pull-up enabled > + str r1, [r0, #0x8] > + > + ldr r1, [r0, #0x4] > + orr r1, r1, #(1 << 7) @ 7 = 7 * 1-bit > + str r1, [r0, #0x4] > + > + mov pc, lr > + nop > + nop > + nop > + > +system_clock_init: > + ldr r0, =S5PC210_CLOCK_BASE > + > + /* APLL(1), MPLL(1), CORE(0), HPM(0) */ > + ldr r1, =0x0101 > + ldr r2, =0x14200 @ CLK_SRC_CPU > + str r1, [r0, r2] > + > + /* wait ?us */ > + mov r1, #0x10000 > +1: subs r1, r1, #1 > + bne 1b > + > + /* > + * CLK_SRC_TOP0 > + * MUX_ONENAND_SEL[28] 0: DOUT133, 1: DOUT166 > + * MUX_VPLL_SEL[8] 0: FINPLL, 1: FOUTVPLL > + * MUX_EPLL_SEL[4] 0: FINPLL, 1: FOUTEPLL > + */ > + ldr r1, =0x10000110 > + ldr r2, =0x0C210 @ CLK_SRC_TOP > + str r1, [r0, r2] > + > + /* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */ > + ldr r1, =0x0066666 > + ldr r2, =0x0C240 @ CLK_SRC_FSYS > + str r1, [r0, r2] > + /* UART[0:5], PWM: SCLKMPLL(6) */ > + ldr r1, =0x6666666 > + ldr r2, =0x0C250 @ CLK_SRC_PERIL0_OFFSET > + str r1, [r0, r2] > + > + /* CPU0: CORE, COREM0, COREM1, PERI, ATB, PCLK_DBG, APLL */ > + ldr r1, =0x0133730 > + ldr r2, =0x14500 @ CLK_DIV_CPU0 > + str r1, [r0, r2] > + /* CPU1: COPY, HPM */ > + ldr r1, =0x03 > + ldr r2, =0x14504 @ CLK_DIV_CPU1 > + str r1, [r0, r2] > + /* DMC0: ACP, ACP_PCLK, DPHY, DMC, DMCD, DMCP, COPY2 CORE_TIMER */ > + ldr r1, =0x13111113 > + ldr r2, =0x10500 @ CLK_DIV_DMC0 > + str r1, [r0, r2] > + /* DMC1: PWI, DVSEM, DPM */ > + ldr r1, =0x01010100 > + ldr r2, =0x10504 @ CLK_DIV_DMC1 > + str r1, [r0, r2] > + /* LEFTBUS: GDL, GPL */ > + ldr r1, =0x13 > + ldr r2, =0x04500 @ CLK_DIV_LEFTBUS > + str r1, [r0, r2] > + /* RIGHHTBUS: GDR, GPR */ > + ldr r1, =0x13 > + ldr r2, =0x08500 @ CLK_DIV_RIGHTBUS > + str r1, [r0, r2] > + /* > + * CLK_DIV_TOP > + * ONENAND_RATIOD[18:16]: 0 SCLK_ONENAND = MOUTONENAND / (n + 1) > + * ACLK_200, ACLK_100, ACLK_160, ACLK_133, > + */ > + ldr r1, =0x00005473 > + ldr r2, =0x0C510 @ CLK_DIV_TOP > + str r1, [r0, r2] > + /* MMC[0:1] */ > + ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ > + ldr r2, =0x0C544 @ CLK_DIV_FSYS1 > + str r1, [r0, r2] > + /* MMC[2:3] */ > + ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */ > + ldr r2, =0x0C548 @ CLK_DIV_FSYS2 > + str r1, [r0, r2] > + /* MMC4 */ > + ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */ > + ldr r2, =0x0C54C @ CLK_DIV_FSYS3 > + str r1, [r0, r2] > + /* UART[0:5] */ > + ldr r1, =0x774777 > + ldr r2, =0x0C550 @ CLK_DIV_PERIL0 > + str r1, [r0, r2] > + /* SLIMBUS: ???, PWM */ > + ldr r1, =0x8 > + ldr r2, =0x0C55C @ CLK_DIV_PERIL3 > + str r1, [r0, r2] > + > + /* PLL Setting */ > + ldr r1, =0x1C20 > + ldr r2, =0x14000 @ APLL_LOCK > + str r1, [r0, r2] > + ldr r2, =0x14008 @ MPLL_LOCK > + str r1, [r0, r2] > + ldr r2, =0x0C010 @ EPLL_LOCK > + str r1, [r0, r2] > + ldr r2, =0x0C020 @ VPLL_LOCK > + str r1, [r0, r2] > + > + /* APLL */ > + ldr r1, =0x8000001c > + ldr r2, =0x14104 @ APLL_CON1 > + str r1, [r0, r2] > + ldr r1, =0x80c80601 @ 800MHz > + ldr r2, =0x14100 @ APLL_CON0 > + str r1, [r0, r2] > + /* MPLL */ > + ldr r1, =0x8000001C > + ldr r2, =0x1410C @ MPLL_CON1 > + str r1, [r0, r2] > + ldr r1, =0x80c80601 @ 800MHz > + ldr r2, =0x14108 @ MPLL_CON0 > + str r1, [r0, r2] > + /* EPLL */ > + ldr r1, =0x0 > + ldr r2, =0x0C114 @ EPLL_CON1 > + str r1, [r0, r2] > + ldr r1, =0x80300302 @ 96MHz > + ldr r2, =0x0C110 @ EPLL_CON0 > + str r1, [r0, r2] > + /* VPLL */ > + ldr r1, =0x11000400 > + ldr r2, =0x0C124 @ VPLL_CON1 > + str r1, [r0, r2] > + ldr r1, =0x80350302 @ 108MHz > + ldr r2, =0x0C120 @ VPLL_CON0 > + str r1, [r0, r2] > + > + /* > + * SMMUJPEG[11], JPEG[6], CSIS1[5] : 0111 1001 > + * Turn off all > + */ > + ldr r1, =0xFFF80000 > + ldr r2, =0x0C920 @ CLK_GATE_IP_CAM > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFFC0 > + ldr r2, =0x0C924 @ CLK_GATE_IP_VP > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFFE0 > + ldr r2, =0x0C928 @ CLK_GATE_IP_MFC > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFFFC > + ldr r2, =0x0C92C @ CLK_GATE_IP_G3D > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFC00 > + ldr r2, =0x0C930 @ CLK_GATE_IP_IMAGE > + str r1, [r0, r2] > + > + /* DSIM0[3], MDNIE0[2], MIE0[1] : 0001 */ > + ldr r1, =0xFFFFFFF1 > + ldr r2, =0x0C934 @ CLK_GATE_IP_LCD0 > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFFC0 > + ldr r2, =0x0C938 @ CLK_GATE_IP_LCD1 > + str r1, [r0, r2] > + > + /* > + * SMMUPCIE[18], NFCON[16] : 1111 1010 > + * PCIE[14], SATA[10], SDMMC43[9:8] : 1011 1000 > + * SDMMC1[6], TSI[4], SATAPHY[3], PCIEPHY[2] : 1010 0011 > + */ > + ldr r1, =0xFFFAB8A3 > + ldr r2, =0x0C940 @ CLK_GATE_IP_FSYS > + str r1, [r0, r2] > + > + /* Turn off all */ > + ldr r1, =0xFFFFFFFC > + ldr r2, =0x0C94C @ CLK_GATE_IP_GPS > + str r1, [r0, r2] > + > + /* > + * AC97[27], SPDIF[26], SLIMBUS[25] : 1111 0001 > + * I2C2[8] : 1111 1110 > + */ > + ldr r1, =0xF1FFFEFF > + ldr r2, =0x0C950 @ CLK_GATE_IP_PERIL > + str r1, [r0, r2] > + > + /* > + * KEYIF[16] : 1111 1110 > + */ > + ldr r1, =0xFFFEFFFF > + ldr r2, =0x0C960 @ CLK_GATE_IP_PERIR > + str r1, [r0, r2] > + > + /* LCD1[5], G3D[3], MFC[2], TV[1] : 1101 0001 */ > + ldr r1, =0xFFFFFFD1 > + ldr r2, =0x0C970 @ CLK_GATE_BLOCK > + str r1, [r0, r2] > + mov pc, lr > + nop > + nop > + nop > + > +system_power_init: > + ldr r0, =S5PC210_POWER_BASE @ 0x10020000 > + > + ldr r2, =0x330C @ PS_HOLD_CONTROL > + ldr r1, [r0, r2] > + orr r1, r1, #(0x3 << 8) @ Data High, Output En > + str r1, [r0, r2] > + > + /* Power Down */ > + add r2, r0, #0x3000 > + str r5, [r2, #0xC20] @ TV_CONFIGURATION > + str r5, [r2, #0xC40] @ MFC_CONFIGURATION > + str r5, [r2, #0xC60] @ G3D_CONFIGURATION > + str r5, [r2, #0xCA0] @ LCD1_CONFIGURATION > + str r5, [r2, #0xCE0] @ GPS_CONFIGURATION > + > + mov pc, lr > + nop > + nop > + nop > + > +tzpc_init: > + ldr r0, =0x10110000 > + mov r1, #0x0 > + str r1, [r0] > + mov r1, #0xff > + str r1, [r0, #0x0804] > + str r1, [r0, #0x0810] > + str r1, [r0, #0x081C] > + str r1, [r0, #0x0828] > + > + ldr r0, =0x10120000 > + mov r1, #0x0 > + str r1, [r0] > + mov r1, #0xff > + str r1, [r0, #0x0804] > + str r1, [r0, #0x0810] > + str r1, [r0, #0x081C] > + str r1, [r0, #0x0828] > + > + ldr r0, =0x10130000 > + mov r1, #0x0 > + str r1, [r0] > + mov r1, #0xff > + str r1, [r0, #0x0804] > + str r1, [r0, #0x0810] > + str r1, [r0, #0x081C] > + str r1, [r0, #0x0828] > + > + ldr r0, =0x10140000 > + mov r1, #0x0 > + str r1, [r0] > + mov r1, #0xff > + str r1, [r0, #0x0804] > + str r1, [r0, #0x0810] > + str r1, [r0, #0x081C] > + str r1, [r0, #0x0828] > + > + ldr r0, =0x10150000 > + mov r1, #0x0 > + str r1, [r0] > + mov r1, #0xff > + str r1, [r0, #0x0804] > + str r1, [r0, #0x0810] > + str r1, [r0, #0x081C] > + str r1, [r0, #0x0828] > + > + mov pc, lr > diff --git a/board/samsung/nuri/nuri.c b/board/samsung/nuri/nuri.c > new file mode 100644 > index 0000000..4a48526 > --- /dev/null > +++ b/board/samsung/nuri/nuri.c > @@ -0,0 +1,201 @@ > +/* > + * Copyright (C) 2011 Samsung Electronics > + * Minkyu Kang <mk7.k...@samsung.com> > + * Kyungmin Park <kyungmin.p...@samsung.com> > + * Łukasz Majewski <l.majew...@samsung.com> > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#include <common.h> > +#include <asm/io.h> > +#include <asm/arch/adc.h> > +#include <asm/arch/gpio.h> > +#include <asm/arch/mmc.h> > + > +DECLARE_GLOBAL_DATA_PTR; > + > +struct s5pc210_gpio_part1 *gpio1; > +struct s5pc210_gpio_part2 *gpio2; > +static unsigned int board_rev; > + > +u32 get_board_rev(void) > +{ > + return board_rev; > +} > + > +static void check_hw_revision(void); > + > +int board_init(void) > +{ > + gpio1 = (struct s5pc210_gpio_part1 *) S5PC210_GPIO_PART1_BASE; > + gpio2 = (struct s5pc210_gpio_part2 *) S5PC210_GPIO_PART2_BASE; > + > + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; > + > + check_hw_revision(); > + printf("HW Revision:\t0x%x\n", board_rev); > + > + return 0; > +} > + > +int dram_init(void) > +{ > + gd->ram_size = \ > + get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + > + get_ram_size((long *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE) + > + get_ram_size((long *)PHYS_SDRAM_3, PHYS_SDRAM_3_SIZE) + > + get_ram_size((long *)PHYS_SDRAM_4, PHYS_SDRAM_4_SIZE); > + > + return 0; > +} > + > +void dram_init_banksize(void) > +{ > + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; > + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; > please put ram size validation. > + gd->bd->bi_dram[1].start = PHYS_SDRAM_2; > + gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE; > + gd->bd->bi_dram[2].start = PHYS_SDRAM_3; > + gd->bd->bi_dram[2].size = PHYS_SDRAM_3_SIZE; > + gd->bd->bi_dram[3].start = PHYS_SDRAM_4; > + gd->bd->bi_dram[3].size = PHYS_SDRAM_4_SIZE; > +} > + > +static unsigned int get_hw_revision(void) > +{ > + int hwrev = 0; > + int i; > + > + /* NFC_EN: GPL2[6]: output high - early enable for board type > chcking */ > + s5p_gpio_direction_output(&gpio2->l2, 6, 1); > + > + /* HW_REV[0:3]: GPE1[0:3] */ > + for (i = 0; i < 4; i++) { > + s5p_gpio_direction_input(&gpio1->e1, i); > + s5p_gpio_set_pull(&gpio1->e1, i, GPIO_PULL_NONE); > + } > + > + udelay(10); > + > + for (i = 0; i < 4; i++) > + hwrev |= (s5p_gpio_get_value(&gpio1->e1, i) << i); > + > + debug("hwrev 0x%x\n", hwrev); > + > + return hwrev; > +} > + > +static void check_hw_revision(void) > +{ > + board_rev = get_hw_revision(); > +} > + > +#ifdef CONFIG_DISPLAY_BOARDINFO > +int checkboard(void) > +{ > + puts("Board:\tExynos4 Nuri\n"); > + return 0; > +} > +#endif > + > +#ifdef CONFIG_GENERIC_MMC > +int board_mmc_init(bd_t *bis) > +{ > + int i, err; > + > + /* MASSMEMORY_EN: GPL[1] -> output LOW */ > + s5p_gpio_direction_output(&gpio2->l1, 1, 0); > + s5p_gpio_set_pull(&gpio2->l1, 1, GPIO_PULL_NONE); > + > + /* > + * eMMC GPIO: > + * SDR 8-bit@48MHz at MMC0 > + * GPK0[0] SD_0_CLK(2) > + * GPK0[1] SD_0_CMD(2) > + * GPK0[2] SD_0_CDn -> Not used > + * GPK0[3:6] SD_0_DATA[0:3](2) > + * GPK1[3:6] SD_0_DATA[0:3](3) > + * > + * DDR 4-bit@26MHz at MMC4 > + * GPK0[0] SD_4_CLK(3) > + * GPK0[1] SD_4_CMD(3) > + * GPK0[2] SD_4_CDn -> Not used > + * GPK0[3:6] SD_4_DATA[0:3](3) > + * GPK1[3:6] SD_4_DATA[4:7](4) > + */ > + for (i = 0; i < 7; i++) { > + if (i == 2) > + continue; > + /* GPK0[0:6] special function 2 */ > + s5p_gpio_cfg_pin(&gpio2->k0, i, GPIO_FUNC(0x2)); > + /* GPK0[0:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k0, i, GPIO_PULL_NONE); > + /* GPK0[0:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k0, i, GPIO_DRV_4X); > + } > + > + for (i = 3; i < 7; i++) { > + /* GPK1[3:6] special function 3 */ > + s5p_gpio_cfg_pin(&gpio2->k1, i, GPIO_FUNC(0x3)); > + /* GPK1[3:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k1, i, GPIO_PULL_NONE); > + /* GPK1[3:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k1, i, GPIO_DRV_4X); > + } > + > + /* > + * MMC device init > + * mmc0 : eMMC (8-bit buswidth) > + * mmc2 : SD card (4-bit buswidth) > + */ > + err = s5p_mmc_init(0, 8); > + > + /* T-flash detect */ > + s5p_gpio_cfg_pin(&gpio2->x3, 3, GPIO_IRQ); > + s5p_gpio_set_pull(&gpio2->x3, 3, GPIO_PULL_UP); > + > + /* > + * Check the T-flash detect pin > + * GPX3[3] T-flash detect pin > + */ > + if (!s5p_gpio_get_value(&gpio2->x3, 3)) { > + /* > + * SD card GPIO: > + * GPK2[0] SD_2_CLK(2) > + * GPK2[1] SD_2_CMD(2) > + * GPK2[2] SD_2_CDn -> Not used > + * GPK2[3:6] SD_2_DATA[0:3](2) > + */ > + for (i = 0; i < 7; i++) { > + if (i == 2) > + continue; > + /* GPK2[0:6] special function 2 */ > + s5p_gpio_cfg_pin(&gpio2->k2, i, GPIO_FUNC(0x2)); > + /* GPK2[0:6] pull disable */ > + s5p_gpio_set_pull(&gpio2->k2, i, GPIO_PULL_NONE); > + /* GPK2[0:6] drv 4x */ > + s5p_gpio_set_drv(&gpio2->k2, i, GPIO_DRV_4X); > + } > + err = s5p_mmc_init(2, 4); > + } > + > + return err; > +} > +#endif > diff --git a/boards.cfg b/boards.cfg > index 604becf..6ae4f3d 100644 > --- a/boards.cfg > +++ b/boards.cfg > @@ -189,6 +189,7 @@ omap4_panda arm armv7 > panda ti > omap4_sdp4430 arm armv7 sdp4430 > ti omap4 > s5p_goni arm armv7 goni > samsung s5pc1xx > smdkc100 arm armv7 smdkc100 > samsung s5pc1xx > +exynos4_nuri arm armv7 nuri > samsung s5pc2xx > origen arm armv7 origen > samsung s5pc2xx > s5pc210_universal arm armv7 universal_c210 > samsung s5pc2xx > smdkv310 arm armv7 smdkv310 > samsung s5pc2xx > diff --git a/include/configs/exynos4_nuri.h > b/include/configs/exynos4_nuri.h > new file mode 100644 > index 0000000..813b301 > --- /dev/null > +++ b/include/configs/exynos4_nuri.h > @@ -0,0 +1,209 @@ > +/* > + * Copyright (C) 2011 Samsung Electronics > + * Łukasz Majewski <l.majew...@samsung.com> > + * > + * Configuation settings for the SAMSUNG Universal (s5pc100) board. > + * > + * See file CREDITS for list of people who contributed to this > + * project. > + * > + * This program is free software; you can redistribute it and/or > + * modify it under the terms of the GNU General Public License as > + * published by the Free Software Foundation; either version 2 of > + * the License, or (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, write to the Free Software > + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, > + * MA 02111-1307 USA > + */ > + > +#ifndef __CONFIG_H > +#define __CONFIG_H > + > +/* > + * High Level Configuration Options > + * > + */ > +#define CONFIG_SAMSUNG /* in a SAMSUNG core */ > +#define CONFIG_S5P /* which is in a S5P Family */ > +#define CONFIG_S5PC210 /* which is in a S5PC210 */ > +#define CONFIG_NURI /* working with NURI */ > + > +#define CONFIG_MACH_TYPE 3379 /* NURI mach type */ > Please use CONFIG_MACH_NURI instead of hard coding it. It is defined in ./arch/arm/include/asm/mach-types.h > + > +#include <asm/arch/cpu.h> /* get chip and board defs */ > + > +#define CONFIG_ARCH_CPU_INIT > +#define CONFIG_DISPLAY_CPUINFO > +#define CONFIG_DISPLAY_BOARDINFO > + > +/* Keep L2 Cache Disabled */ > +#define CONFIG_SYS_L2CACHE_OFF 1 > + > +#define CONFIG_SYS_SDRAM_BASE 0x40000000 > +#define CONFIG_SYS_TEXT_BASE 0x44800000 > + > +/* input clock of PLL: Universal has 24MHz input clock at S5PC210 */ > +#define CONFIG_SYS_CLK_FREQ_C210 24000000 > + > +#define CONFIG_SETUP_MEMORY_TAGS > +#define CONFIG_CMDLINE_TAG > +#define CONFIG_INITRD_TAG > +#define CONFIG_REVISION_TAG > +#define CONFIG_CMDLINE_EDITING > + > +/* Size of malloc() pool */ > +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20)) > + > +/* select serial console configuration */ > +#define CONFIG_SERIAL_MULTI > +#define CONFIG_SERIAL2 /* use SERIAL 2 */ > +#define CONFIG_BAUDRATE 115200 > + > +/* MMC */ > +#define CONFIG_GENERIC_MMC > +#define CONFIG_MMC > +#define CONFIG_S5P_MMC > + > +/* PWM */ > +#define CONFIG_PWM > + > +/* It should define before config_cmd_default.h */ > +#define CONFIG_SYS_NO_FLASH > + > +/* Command definition */ > +#include <config_cmd_default.h> > + > +#undef CONFIG_CMD_FPGA > +#undef CONFIG_CMD_MISC > +#undef CONFIG_CMD_NET > +#undef CONFIG_CMD_NFS > +#undef CONFIG_CMD_XIMG > +#define CONFIG_CMD_CACHE > +#define CONFIG_CMD_MMC > +#define CONFIG_CMD_FAT > + > +#define CONFIG_BOOTDELAY 2 > +#define CONFIG_ZERO_BOOTDELAY_CHECK > + > +#define CONFIG_BOOTARGS "Please use defined boot" > +#define CONFIG_BOOTCOMMAND "run mmcboot" > +#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" > + > +#define CONFIG_BOOTBLOCK "10" > +#define CONFIG_UBIBLOCK "9" > + > +#define CONFIG_ENV_UBIFS_OPTION " > rootflags=bulk_read,no_chk_data_crc " > + > +#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" > + > +#define CONFIG_ENV_OVERWRITE > +#define CONFIG_SYS_CONSOLE_INFO_QUIET > +#define CONFIG_SYS_CONSOLE_IS_IN_ENV > + > +#define MBRPARTS_DEFAULT "20M(permanent)"\ > + ",20M(boot)"\ > + ",1G(system)"\ > + ",100M(swap)"\ > + ",-(UMS)\0" > + > +#define CONFIG_EXTRA_ENV_SETTINGS \ > + "bootk=" \ > + "run loaduimage; bootm 0x40007FC0\0" \ > + "updatemmc=" \ > + "mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \ > + "mmc boot 0 1 1 0\0" \ > + "updatebackup=" \ > + "mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \ > + "mmc boot 0 1 1 0\0" \ > + "updatebootb=" \ > + "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ > + "lpj=lpj=3981312\0" \ > + "nfsboot=" \ > + "set bootargs root=/dev/nfs rw " \ > + "nfsroot=${nfsroot},nolock,tcp " \ > + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ > + "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ > + "; run bootk\0" \ > + "ramfsboot=" \ > + "set bootargs root=/dev/ram0 rw rootfstype=ext2 " \ > + "${console} ${meminfo} " \ > + "initrd=0x43000000,8M ramdisk=8192\0" \ > + "mmcboot=" \ > + "set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ > + "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; > " \ > + "run loaduimage; bootm 0x40007FC0\0" \ > + "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ > + "boottrace=setenv opts initcall_debug; run bootcmd\0" \ > + "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ > + "verify=n\0" \ > + "rootfstype=ext4\0" \ > + "console=" CONFIG_DEFAULT_CONSOLE \ > + "mbrparts=" MBRPARTS_DEFAULT \ > + "meminfo=crashkernel=32M@0x50000000\0" \ > + "nfsroot=/nfsroot/arm\0" \ > + "bootblock=" CONFIG_BOOTBLOCK "\0" \ > + "ubiblock=" CONFIG_UBIBLOCK" \0" \ > + "loaduimage=fatload mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 > uImage\0" \ > + "mmcdev=0\0" \ > + "mmcbootpart=2\0" \ > + "mmcrootpart=5\0" \ > + "opts=always_resume=1" > + > +/* Miscellaneous configurable options */ > +#define CONFIG_SYS_LONGHELP /* undef to save memory */ > +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ > +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " > +#define CONFIG_SYS_PROMPT "Nuri # " > +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ > +#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */ > +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ > +/* Boot Argument Buffer Size */ > +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE > +/* memtest works on */ > +#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE > +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) > +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) > + > +#define CONFIG_SYS_HZ 1000 > + > +/* valid baudrates */ > +#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, > 115200 } > + > +/* Stack sizes */ > +#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */ > + > +/* Nuri has 2 banks of DRAM -> support bank swapping */ > +#define CONFIG_NR_DRAM_BANKS 4 > As per comment Nuri has 2 banks of DRAM, But configuration happens for 4 banks. > +#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */ > +#define PHYS_SDRAM_1_SIZE (256 << 20) /* 256 MB in CS 0 > */ > +#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */ > +#define PHYS_SDRAM_2_SIZE (256 << 20) /* 256 MB in CS 0 > */ > +#define PHYS_SDRAM_3 0x60000000 > +#define PHYS_SDRAM_3_SIZE (256 << 20) > +#define PHYS_SDRAM_4 0x70000000 > +#define PHYS_SDRAM_4_SIZE (256 << 20) > + > +#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram > console */ > + > +#define CONFIG_SYS_MONITOR_BASE 0x00000000 > +#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 > sectors */ > + > +#define CONFIG_ENV_IS_IN_MMC > +#define CONFIG_SYS_MMC_ENV_DEV 0 > +#define CONFIG_ENV_SIZE 4096 > +#define CONFIG_ENV_OFFSET ((32 - 4) << 10)/* 32KiB - 4KiB */ > + > +#define CONFIG_DOS_PARTITION > + > +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - > GENERATED_GBL_DATA_SIZE) > + > +#define CONFIG_SYS_CACHELINE_SIZE 32 > + > +#endif /* __CONFIG_H */ > -- > 1.7.2.3 > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot > -- with warm regards, Chander Kashyap
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