On Nov 20, 2011, at 12:01 PM, York Sun wrote: > Erratum A-003474: Internal DDR calibration circuit is not supported > > Impact: > Experience shows no significant benefit to device operation with > auto-calibration enabled versus it disabled. To ensure consistent timing > results, Freescale recommends this feature be disabled in future customer > products. There should be no impact to parts that are already operating > in the field. > > Workaround: > Prior to setting DDR_SDRAM_CFG[MEM_EN]=1, do the following: > 1. Write a value of 0x0000_0015 to the register at offset > CCSRBAR + DDR OFFSET + 0xf30 > 2. Write a value of 0x2400_0000 to the register at offset > CCSRBAR + DDR OFFSET + 0xf54 > > Signed-off-by: York Sun <york...@freescale.com> > --- > arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ > arch/powerpc/cpu/mpc85xx/ddr-gen3.c | 5 +++++ > arch/powerpc/include/asm/config_mpc85xx.h | 7 +++++++ > 3 files changed, 15 insertions(+), 0 deletions(-)
applied to 85xx - k _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot