Earliar ARM clock frequency was calculated by:
MOUTAPLL/(DIVAPLL + 1) which is actually returning SCLKAPLL.
It is fixed by calcuating it as follows:
ARMCLK=MOUTCORE/(DIVCORE + 1)/DIVCORE2 + 1)
Signed-off-by: Chander Kashyap <chander.kash...@linaro.org>
---
arch/arm/cpu/armv7/exynos/clock.c | 9 ++++++---
1 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c
b/arch/arm/cpu/armv7/exynos/clock.c
index 64de262..17ff012 100644
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -103,14 +103,17 @@ static unsigned long exynos4_get_arm_clk(void)
(struct exynos4_clock *)samsung_get_base_clock();
unsigned long div;
unsigned long dout_apll;
- unsigned int apll_ratio;
+ unsigned int core_ratio;
+ unsigned int core2_ratio;
div = readl(&clk->div_cpu0);
/* APLL_RATIO: [26:24] */
- apll_ratio = (div >> 24) & 0x7;
+ core_ratio = (div >> 0) & 0x7;
+ core2_ratio = (div >> 28) & 0x7;
- dout_apll = get_pll_clk(APLL) / (apll_ratio + 1);
+ dout_apll = get_pll_clk(APLL) / (core_ratio + 1);
+ dout_apll /= (core2_ratio + 1);
return dout_apll;
}
--
1.7.5.4
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