Simon Glass wrote at Wednesday, December 21, 2011 1:03 PM: > When the data cache is enabled we must flush on write and invalidate > on read. We also check that buffers are aligned to data cache lines > boundaries. With recent work in U-Boot this should generally be the case > but the warnings will catch problems. > > Signed-off-by: Simon Glass <s...@chromium.org>
Conceptually this seems fine, but shouldn't the MMC driver core be doing the cache management, so all platforms without cache coherency can benefit from it? -- nvpublic _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
