Hi Simon, On 04/01/12 16:38, Simon Glass wrote: > Hi Graeme, > > On Sun, Jan 1, 2012 at 8:09 PM, Graeme Russ <graeme.r...@gmail.com> wrote: >> >> Signed-off-by: Graeme Russ <graeme.r...@gmail.com> >> --- >> arch/x86/cpu/cpu.c | 18 +++++++++++++++--- >> arch/x86/include/asm/u-boot-x86.h | 1 + >> arch/x86/lib/board.c | 1 + >> 3 files changed, 17 insertions(+), 3 deletions(-) >> >> diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c >> index e7a5fc0..4351f20 100644 >> --- a/arch/x86/cpu/cpu.c >> +++ b/arch/x86/cpu/cpu.c >> @@ -140,6 +140,14 @@ int cpu_init_f(void) __attribute__((weak, >> alias("x86_cpu_init_f"))); >> >> int x86_cpu_init_r(void) >> { >> + /* Initialize core interrupt and exception functionality of CPU */ >> + cpu_init_interrupts(); >> + return 0; >> +} > > This doesn't seem to match the commit title.
Well git diffs do some weird things sometimes - if you look further down, you'll see that there isn't actually a code change here > >> +int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); >> + >> +void x86_enable_caches(void) >> +{ >> const u32 nw_cd_rst = ~(X86_CR0_NW | X86_CR0_CD); >> >> /* turn on the cache and disable write through */ >> @@ -147,12 +155,16 @@ int x86_cpu_init_r(void) >> "andl %0, %%eax\n" >> "movl %%eax, %%cr0\n" >> "wbinvd\n" : : "i" (nw_cd_rst) : "eax"); >> +} >> +void enable_caches(void) __attribute__((weak, alias("x86_enable_caches"))); >> + >> +int x86_init_cache(void) >> +{ >> + enable_caches(); > > Does this enable both I and D caches? Yes - In x86, the I & D caches are turned on and off simultaneously. Also, some x86 CPU's only have a single unified cache anyway >> >> - /* Initialize core interrupt and exception functionality of CPU */ >> - cpu_init_interrupts(); >> return 0; >> } >> -int cpu_init_r(void) __attribute__((weak, alias("x86_cpu_init_r"))); >> +int init_cache(void) __attribute__((weak, alias("x86_init_cache"))); >> >> int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) >> { >> diff --git a/arch/x86/include/asm/u-boot-x86.h >> b/arch/x86/include/asm/u-boot-x86.h >> index 5540d51..878a1ee 100644 >> --- a/arch/x86/include/asm/u-boot-x86.h >> +++ b/arch/x86/include/asm/u-boot-x86.h >> @@ -39,6 +39,7 @@ int x86_cpu_init_f(void); >> int cpu_init_f(void); >> void init_gd(gd_t *id, u64 *gdt_addr); >> void setup_gdt(gd_t *id, u64 *gdt_addr); >> +int init_cache(void); >> >> /* cpu/.../timer.c */ >> void timer_isr(void *); >> diff --git a/arch/x86/lib/board.c b/arch/x86/lib/board.c >> index 4e54dba..ffddfbe 100644 >> --- a/arch/x86/lib/board.c >> +++ b/arch/x86/lib/board.c >> @@ -140,6 +140,7 @@ init_fnc_t *init_sequence_f[] = { >> >> init_fnc_t *init_sequence_r[] = { >> copy_gd_to_ram, >> + init_cache, > > Would enable_caches be a better name? Getting the cache working is a two step process - init_cache() sets up the cache regions, typically using the Memory Type Range Registers (MTRRs) enable_caches() actually turns the CPU cache on Regards, Graeme _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot