Hi Albert, On Saturday, January 14, 2012, Albert ARIBAUD <albert.u.b...@aribaud.net> wrote: > Le 12/01/2012 07:29, Sughosh Ganu a écrit : >> >> On Thu Jan 12, 2012 at 06:56:01AM +0100, Christian Riesch wrote: >>> >>> On Wednesday, January 11, 2012, Marek Vasut<marek.va...@gmail.com> wrote: >> >> <snip> >> >>>>> RBL executes an AIS script. Sughosh, could you please explain what your >>> >>> AIS >>>>> >>>>> does or how you create it? >>>> >>>> So basically, this SPL business can be avoided and this all can be done >>> >>> in a >>>> >>>> standard way? >>> >>> I don't know, I never had to deal with booting from NAND. I was just >>> wondering what Sughosh's AIS is doing that he gets these SPL problems. >>> Christian >> >> I have checked my ais ini file, and it does the normal pll/ddr >> settings. I think it is the rbl which might be turning the cache >> ON. > > I do understand it is ROM code so no change can be done to it, but that a bootloader pass control to its payload with the cache still enabled and, worse yet, dirty, is Bad(tm). > > Can the AIS not be augmented with instructions to flush and disable the cache?
I checked the AIS documentation and I don't think this can be done... AIS has a command to write arbitrary memory regions, but not registers. Christian
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