This patchset does bug fixes for Synopsys' designware ethernet controller driver in SPEAr SoCs.
Changes since V1: - Added comment to explain the ratinale behind restoring hw mac address - Undefined TRUE/FALSE and used 1/0 instead while configuring phy Amit Virdi (1): net/designware: Change timeout loop implementation Armando Visconti (2): net/designware: Consecutive writes must have delay net/designware: Set ANAR to 0x1e1 Vikas Manocha (1): net/designware: Program phy registers when auto-negotiation is ON Vipin KUMAR (3): net/designware: Fix to restore hw mac address net/designware: Fix the max frame length size net/designware: Phy address fix Vipin Kumar (1): net/designware: Try configuring phy on each dw_eth_init drivers/net/designware.c | 128 ++++++++++++++++++++++++++++++++-------------- drivers/net/designware.h | 3 +- 2 files changed, 92 insertions(+), 39 deletions(-) -- 1.7.2.2 _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
