Re: [U-Boot] [PATCH 2/2] i.MX6: mx6q_sabrelite: add SATA bindings

[Eric Nelson]

On 03/26/2012 01:35 AM, Stefano Babic wrote:
On 26/03/2012 01:00, Eric Nelson wrote:
V2 has been stripped of the board-independent changes and
uses clrsetbits_le32() instead of twiddling bits by hand.
Signed-off-by: Eric Nelson<eric.nel...@boundarydevices.com>
---

Hi Eric,

  board/freescale/mx6qsabrelite/mx6qsabrelite.c |   32 +++++++++++++++++++++++++
  include/configs/mx6qsabrelite.h               |   13 ++++++++++
  2 files changed, 45 insertions(+), 0 deletions(-)

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index 1d09a72..afb1245 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -25,6 +25,8 @@
  #include<asm/arch/imx-regs.h>
  #include<asm/arch/mx6x_pins.h>
  #include<asm/arch/iomux-v3.h>
+#include<asm/arch/ccm_regs.h>
+#include<asm/arch/clock.h>
  #include<asm/errno.h>
  #include<asm/gpio.h>
  #include<mmc.h>
@@ -267,6 +269,32 @@ int board_eth_init(bd_t *bis)
        return 0;
  }

+#ifdef CONFIG_CMD_SATA
+
+int setup_sata(void)
+{
+       int rval = enable_sata_clock();

What about to return at this point if there is an error ?


I'm not sure I understand. Do you mean re-structure the code with
two returns like this?

diff --git a/board/freescale/mx6qsabrelite/mx6qsabrelite.c 
b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
index afb1245..0d625af 100644
--- a/board/freescale/mx6qsabrelite/mx6qsabrelite.c
+++ b/board/freescale/mx6qsabrelite/mx6qsabrelite.c
@@ -273,23 +273,23 @@ int board_eth_init(bd_t *bis)

 int setup_sata(void)
 {
+       struct iomuxc_base_regs *const iomuxc_regs
+               = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
        int rval = enable_sata_clock();
-       if (rval == 0) {
-               struct iomuxc_base_regs *const iomuxc_regs
-                       = (struct iomuxc_base_regs *) IOMUXC_BASE_ADDR;
-               clrsetbits_le32(&iomuxc_regs->gpr[13],
-                               IOMUXC_GPR13_SATA_MASK,
-                               IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
-                               |IOMUXC_GPR13_SATA_PHY_7_SATA2M
-                               |IOMUXC_GPR13_SATA_SPEED_3G
-                               |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
-                               |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
-                               |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
-                               |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
-                               |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
-                               |IOMUXC_GPR13_SATA_PHY_1_SLOW);
-               rval = 0;
-       }
+       if (rval)
+               return rval ;
+
+       clrsetbits_le32(&iomuxc_regs->gpr[13],
+                       IOMUXC_GPR13_SATA_MASK,
+                       IOMUXC_GPR13_SATA_PHY_8_RXEQ_3P0DB
+                       |IOMUXC_GPR13_SATA_PHY_7_SATA2M
+                       |IOMUXC_GPR13_SATA_SPEED_3G
+                       |(3<<IOMUXC_GPR13_SATA_PHY_6_SHIFT)
+                       |IOMUXC_GPR13_SATA_SATA_PHY_5_SS_DISABLED
+                       |IOMUXC_GPR13_SATA_SATA_PHY_4_ATTEN_9_16
+                       |IOMUXC_GPR13_SATA_PHY_3_TXBOOST_0P00_DB
+                       |IOMUXC_GPR13_SATA_PHY_2_TX_1P104V
+                       |IOMUXC_GPR13_SATA_PHY_1_SLOW);

        return rval;
 }

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