This commit is an add-on to f6c4191f. There are a few other registers where
consecutive writes must have a delay.
Signed-off-by: Dinh Nguyen <dingu...@altera.com>
---
drivers/net/designware.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index e8e669b..34952c0 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -163,8 +163,8 @@ static int dw_eth_init(struct eth_device *dev, bd_t *bis)
writel(FIXEDBURST | PRIORXTX_41 | BURST_16,
&dma_p->busmode);
- writel(FLUSHTXFIFO | readl(&dma_p->opmode), &dma_p->opmode);
- writel(STOREFORWARD | TXSECONDFRAME, &dma_p->opmode);
+ writel(readl(&dma_p->opmode) | FLUSHTXFIFO | STOREFORWARD | \
+ TXSECONDFRAME, &dma_p->opmode);
conf = FRAMEBURSTENABLE | DISABLERXOWN;
--
1.7.9.5
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