On 06/24/2012 05:17 PM, Marek Vasut wrote:
This prevents the scenario where data cache is on and the device uses DMA to deploy data. In that case, it might not be possible to flush/invalidate data to RAM properly. The other option is to use bounce buffer, but that involves a lot of copying and therefore degrades performance rapidly. Therefore disallow this possibility of unaligned load address altogether if data cache is on.Signed-off-by: Marek Vasut<ma...@denx.de> Cc: Scott Wood<scottw...@freescale.com> --- common/cmd_nand.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/common/cmd_nand.c b/common/cmd_nand.c index a91ccf4..122a91c 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -609,6 +609,8 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) goto usage; addr = (ulong)simple_strtoul(argv[2], NULL, 16); + if (!cacheline_aligned(addr)) + return 1;
You need to check the end address too. Also, I agree with Scott that that this is an un-justifiable restriction on cache-coherent architectures. IMO, such checks should be done in platform specific code where the DMA is being attempted. best regards, Aneesh _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
