Hi Scott and Stefano,
You will find below the newest patch for the NAND flash access problem on the
TX25 module.
I hope this version is fulfilling all your expectations.
Cordially,
Daniel
diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 936186f..08fbb12 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c
@@ -48,6 +48,17 @@
* Reading or writing a 2K or 4K page requires only 1 FDI/FDO cycle.
* Also some of registers are moved and/or changed meaning as seen below.
*/
+/*
+ * NAND Flash access mode on MX25
+ *
+ * The MX25 NAND Flash Controller supports two modes to access the Flash:
+ * a) symmetric mode (one Flash clock cycle per access) or
+ * b) asymmetric mode (two Flash clock cycles per access)
+ *
+ * By default the NAND Flash Controller is configured in the symmetric mode.
+ * To select the asymmetric mode, the configuration option
+ * CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES has to be selected.
+ */
#if defined(CONFIG_MX31) || defined(CONFIG_MX27)
#define MXC_NFC_V1
#elif defined(CONFIG_MX25) || defined(CONFIG_MX35)
@@ -1290,7 +1301,9 @@ static void mxc_setup_config1(void)
uint16_t tmp;
tmp = readw(&host->regs->nfc_config1);
+#ifndef CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES
tmp |= NFC_ONE_CYCLE;
+#endif
tmp |= NFC_4_8N_ECC;
writew(tmp, &host->regs->nfc_config1);
if (host->pagesize_2k)
diff --git a/include/configs/tx25.h b/include/configs/tx25.h
index 6821528..8fa51cb 100644
--- a/include/configs/tx25.h
+++ b/include/configs/tx25.h
@@ -109,6 +109,7 @@
/* NAND */
#define CONFIG_NAND_MXC
#define CONFIG_NAND_MXC_V1_1
+#define CONFIG_SYS_NAND_MXC_NFC_TWO_CYCLES /* 2 cycles to access NAND Flash */
#define CONFIG_MXC_NAND_REGS_BASE (0xBB000000)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE (0xBB000000)
_______________________________________________
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
