Homogenize prg_p naming (the reference manuals are not always self-consistent
for that). Add missing registers. Fix some registers.
Signed-off-by: Benoît Thébaudeau <benoit.thebaud...@advansee.com>
Cc: Stefano Babic <sba...@denx.de>
Cc: Wolfgang Denk <w...@denx.de>
---
.../arch/arm/include/asm/arch-mx25/imx-regs.h | 8 ++++++--
.../arch/arm/include/asm/arch-mx27/imx-regs.h | 2 +-
.../arch/arm/include/asm/arch-mx31/imx-regs.h | 9 +++++++--
.../arch/arm/include/asm/arch-mx35/imx-regs.h | 7 ++++++-
.../arch/arm/include/asm/arch-mx5/imx-regs.h | 6 +++++-
5 files changed, 25 insertions(+), 7 deletions(-)
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/imx-regs.h
index cf925d7..b7b4d07 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx25/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx25/imx-regs.h
@@ -118,8 +118,12 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
- u32 res1[0x1f5];
+ u32 iim_prg_p;
+ u32 iim_scs0;
+ u32 iim_scs1;
+ u32 iim_scs2;
+ u32 iim_scs3;
+ u32 res1[0x1f1];
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx27/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx27/imx-regs.h
index ced5b2a..bfca963 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx27/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx27/imx-regs.h
@@ -197,7 +197,7 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
index 7ddbbd6..c2db85f 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx31/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx31/imx-regs.h
@@ -79,7 +79,7 @@ struct wdog_regs {
u16 wrsr; /* Reset Status */
};
-/* IIM Control Registers */
+/* IIM control registers */
struct iim_regs {
u32 iim_stat;
u32 iim_statm;
@@ -91,11 +91,16 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
};
struct iomuxc_regs {
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h
index 3146006..f75e5c2 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx35/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx35/imx-regs.h
@@ -283,11 +283,16 @@ struct iim_regs {
u32 iim_sdat;
u32 iim_prev;
u32 iim_srev;
- u32 iim_prog_p;
+ u32 iim_prg_p;
u32 iim_scs0;
u32 iim_scs1;
u32 iim_scs2;
u32 iim_scs3;
+ u32 res1[0x1f1];
+ struct fuse_bank {
+ u32 fuse_regs[0x20];
+ u32 fuse_rsvd[0xe0];
+ } bank[3];
};
/* General Purpose Timer (GPT) registers */
diff --git u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/imx-regs.h
u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/imx-regs.h
index 7f66b61..33d2097 100644
--- u-boot-4d3c95f.orig/arch/arm/include/asm/arch-mx5/imx-regs.h
+++ u-boot-4d3c95f/arch/arm/include/asm/arch-mx5/imx-regs.h
@@ -482,7 +482,7 @@ struct iim_regs {
u32 sdat;
u32 prev;
u32 srev;
- u32 preg_p;
+ u32 prg_p;
u32 scs0;
u32 scs1;
u32 scs2;
@@ -491,7 +491,11 @@ struct iim_regs {
struct fuse_bank {
u32 fuse_regs[0x20];
u32 fuse_rsvd[0xe0];
+#if defined(CONFIG_MX51)
} bank[4];
+#elif defined(CONFIG_MX53)
+ } bank[5];
+#endif
};
struct fuse_bank0_regs {
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