On 17.08.2012 22:50, Marek Vasut wrote:
Dear Łukasz Dałek,
+ /* UDC Endpoint Control/Status Registers */
+ uint32_t udccs0; /* 0x010 */
+ uint32_t udccs1; /* 0x014 */
+ uint32_t udccs2; /* 0x018 */
+ uint32_t udccs3; /* 0x01c */
+ uint32_t udccs4; /* 0x020 */
+ uint32_t udccs5; /* 0x024 */
+ uint32_t udccs6; /* 0x028 */
+ uint32_t udccs7; /* 0x02c */
+ uint32_t udccs8; /* 0x030 */
+ uint32_t udccs9; /* 0x034 */
+ uint32_t udccs10; /* 0x038 */
+ uint32_t udccs11; /* 0x03c */
+ uint32_t udccs12; /* 0x040 */
+ uint32_t udccs13; /* 0x044 */
+ uint32_t udccs14; /* 0x048 */
+ uint32_t udccs15; /* 0x04c */
Use array here maybe? ;-)
Yes, array is a good idea.
+ uint32_t uddr9; /* 0x900 */
+ uint8_t reserved14[508];
+ uint32_t uddr11; /* 0xb00 */
+ uint8_t reserved15[124];
+ uint32_t uddr12; /* 0xb80 */
+ uint8_t reserved16[124];
+ uint32_t uddr13; /* 0xc00 */
+ uint8_t reserved17[508];
+ uint32_t uddr14; /* 0xe00 */
+
+} __packed;
You don't need this.
Why? GCC on ARM doesn't align structures?
+#define UDCCFR_AREN (1<< 7) /* ACK response enable (now) */
+#define UDCCFR_ACM (1<< 2) /* ACK control mode (wait for AREN) */
+/* latest pxa255 errata define new "must be one" bits in UDCCFR */
+#define UDCCFR_MB1 (0xff& ~(UDCCFR_AREN | UDCCFR_ACM))
What errata and where? Please document it in the comment. Also, is the register
only 8 bit wide?
Ok, I will document. All registers are 32 bits wide. But some you have to
access like they are 8 bits wide.
Łukasz Dałek
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