This patch adds support for the a3m071 board based on the
MPC5200.
Signed-off-by: Stefan Roese <s...@denx.de>
---
MAINTAINERS | 2 +
board/a3m071/Makefile | 36 ++++
board/a3m071/a3m071.c | 335 +++++++++++++++++++++++++++++++++++++
board/a3m071/mt46v16m16-75.h | 32 ++++
boards.cfg | 1 +
include/configs/a3m071.h | 384 +++++++++++++++++++++++++++++++++++++++++++
6 files changed, 790 insertions(+)
create mode 100644 board/a3m071/Makefile
create mode 100644 board/a3m071/a3m071.c
create mode 100644 board/a3m071/mt46v16m16-75.h
create mode 100644 include/configs/a3m071.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c5a6f2f..d848ffc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -390,6 +390,8 @@ Ricardo Ribalda <ricardo.riba...@uam.es>
Stefan Roese <s...@denx.de>
+ a3m071 MPC5200
+
P3M7448 MPC7448
uc100 MPC857
diff --git a/board/a3m071/Makefile b/board/a3m071/Makefile
new file mode 100644
index 0000000..6f961fb
--- /dev/null
+++ b/board/a3m071/Makefile
@@ -0,0 +1,36 @@
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+include $(TOPDIR)/config.mk
+
+LIB = $(obj)lib$(BOARD).o
+
+COBJS := $(BOARD).o
+
+SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
+OBJS := $(addprefix $(obj),$(COBJS))
+SOBJS := $(addprefix $(obj),$(SOBJS))
+
+$(LIB): $(obj).depend $(OBJS)
+ $(call cmd_link_o_target, $(OBJS))
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################
diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c
new file mode 100644
index 0000000..89ced82
--- /dev/null
+++ b/board/a3m071/a3m071.c
@@ -0,0 +1,335 @@
+/*
+ * (C) Copyright 2003-2004
+ * Wolfgang Denk, DENX Software Engineering, w...@denx.de.
+ *
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jo...@motorola.com.
+ *
+ * (C) Copyright 2006
+ * MicroSys GmbH
+ *
+ * Copyright 2012 Stefan Roese <s...@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <mpc5xxx.h>
+#include <pci.h>
+#include <miiphy.h>
+#include <asm/processor.h>
+#include <asm/io.h>
+
+#include "mt46v16m16-75.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+ (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+static void sdram_start(int hi_addr)
+{
+ long hi_addr_bit = hi_addr ? 0x01000000 : 0;
+ long control = SDRAM_CONTROL | hi_addr_bit;
+
+ /* unlock mode register */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000);
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+#ifdef SDRAM_DDR
+ /* set mode register: extended mode */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE);
+
+ /* set mode register: reset DLL */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000);
+#endif
+
+ /* precharge all banks */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002);
+
+ /* auto refresh */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004);
+
+ /* set mode register */
+ out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE);
+
+ /* normal operation */
+ out_be32((void *)MPC5XXX_SDRAM_CTRL, control);
+}
+#endif
+
+/*
+ * ATTENTION: Although partially referenced initdram does NOT make real use
+ * use of CONFIG_SYS_SDRAM_BASE. The code does not work if
+ * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000.
+ */
+phys_size_t initdram(int board_type)
+{
+ ulong dramsize = 0;
+ ulong dramsize2 = 0;
+ uint svr, pvr;
+#if !defined(CONFIG_SYS_RAMBOOT) && \
+ (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD))
+ ulong test1, test2;
+
+ /* setup SDRAM chip selects */
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */
+ out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */
+
+ /* setup config registers */
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1);
+ out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2);
+
+#ifdef SDRAM_DDR
+ /* set tap delay */
+ out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY);
+#endif
+
+ /* find RAM size using SDRAM CS0 only */
+ sdram_start(0);
+ test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ sdram_start(1);
+ test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
+ if (test1 > test2) {
+ sdram_start(0);
+ dramsize = test1;
+ } else {
+ dramsize = test2;
+ }
+
+ /* memory smaller than 1MB is impossible */
+ if (dramsize < (1 << 20))
+ dramsize = 0;
+
+ /* set SDRAM CS0 size according to the amount of RAM found */
+ if (dramsize > 0) {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG,
+ 0x13 + __builtin_ffs(dramsize >> 20) - 1);
+ } else {
+ out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */
+ }
+#else /* CONFIG_SYS_RAMBOOT */
+
+ /* retrieve size of memory connected to SDRAM CS0 */
+ dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
+ if (dramsize >= 0x13)
+ dramsize = (1 << (dramsize - 0x13)) << 20;
+ else
+ dramsize = 0;
+
+ /* retrieve size of memory connected to SDRAM CS1 */
+ dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF;
+ if (dramsize2 >= 0x13)
+ dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
+ else
+ dramsize2 = 0;
+
+#endif /* CONFIG_SYS_RAMBOOT */
+
+ /*
+ * On MPC5200B we need to set the special configuration delay in the
+ * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM
+ * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190:
+ *
+ * "The SDelay should be written to a value of 0x00000004. It is
+ * required to account for changes caused by normal wafer processing
+ * parameters."
+ */
+ svr = get_svr();
+ pvr = get_pvr();
+ if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4))
+ out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04);
+
+ return dramsize + dramsize2;
+}
+
+static void get_revisions(int *failsavelevel, int *digiboardversion,
+ int *fpgaversion)
+{
+ struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT;
+ u8 val;
+
+ /*
+ * Figure out failsavelevel
+ * see ticket dsvk#59
+ */
+ *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */
+
+ /* read digitalboard-version from TMR[2..4] */
+ val = 0;
+ val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0;
+ val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+ val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+ *digiboardversion = val;
+
+ if (*digiboardversion == 0) {
+ *failsavelevel = 1; /* digiboard-version ok */
+
+ /* read fpga-version from TMR[5..7] */
+ val = 0;
+ val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0;
+ val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0;
+ val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0;
+ *fpgaversion = val;
+
+ if (*fpgaversion == 1)
+ *failsavelevel = 2; /* fpga-version ok */
+ }
+}
+
+/*
+ * This function is called from the SPL U-Boot version for
+ * early init stuff, that needs to be done for OS (e.g. Linux)
+ * booting. Doing it later in the real U-Boot would not work
+ * in case that the SPL U-Boot boots Linux directly.
+ */
+void spl_board_init(void)
+{
+ struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
+ struct mpc5xxx_mmap_ctl *mm =
+ (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR;
+ int digiboardversion;
+ int failsavelevel;
+ int fpgaversion;
+ u32 val;
+
+ get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+ val = in_be32(&mm->ipbi_ws_ctrl);
+
+ /* first clear bits 19..21 (CS3...5) */
+ val &= ~((1 << 19) | (1 << 20) | (1 << 21));
+ if (failsavelevel == 2) {
+ /* FPGA ok */
+ val |= (1 << 19) | (1 << 21);
+ }
+
+ if (failsavelevel >= 1) {
+ /* at least digiboard-version ok */
+ val |= (1 << 20);
+ }
+
+ /* And write new value back to register */
+ out_be32(&mm->ipbi_ws_ctrl, val);
+
+ /*
+ * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG)
+ * as all 3 config versions (failsave level) have the same setup.
+ */
+
+ /*
+ * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see
+ * ticket #60
+ *
+ * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT)
+ * set bit 0(msb) to 1
+ */
+ setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0));
+
+ /* setup GPIOs for status-leds if needed - see ticket #57 */
+ if (failsavelevel > 0) {
+ /* digiboard-version is OK */
+ /* LED is LOW ACTIVE - so deactivate by set output to 1 */
+ gpio->simple_dvo |= 1 << (31 - 12);
+ gpio->simple_dvo |= 1 << (31 - 13);
+ /* set GPIO direction to output */
+ gpio->simple_ddr |= 1 << (31 - 12);
+ gpio->simple_ddr |= 1 << (31 - 13);
+ /* open drain config is set to "normal output" at reset */
+ /* gpio->simple_ode &=~ ( 1 << (31-12) ); */
+ /* gpio->simple_ode &=~ ( 1 << (31-13) ); */
+ /* enable as GPIO */
+ gpio->simple_gpioe |= 1 << (31 - 12);
+ gpio->simple_gpioe |= 1 << (31 - 13);
+ }
+
+ /* setup fpga irq - see ticket #65 */
+ if (failsavelevel > 1) {
+ /*
+ * The main irq initialisation is done in interrupts.c
+ * mpc5xxx_init_irq
+ */
+ struct mpc5xxx_intr *intr =
+ (struct mpc5xxx_intr *)(MPC5XXX_ICTL);
+
+ setbits_be32(&intr->ctrl, 0x08C01801);
+
+ /*
+ * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the
+ * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above
+ */
+ }
+
+}
+
+int checkboard(void)
+{
+ int digiboardversion;
+ int failsavelevel;
+ int fpgaversion;
+
+ get_revisions(&failsavelevel, &digiboardversion, &fpgaversion);
+
+ puts("Board: A3M071\n");
+ printf("Rev: failsave level %u\n", failsavelevel);
+ printf(" digiboard IO version %u\n", digiboardversion);
+ if (failsavelevel > 0) /* only if fpga-version red */
+ printf(" fpga IO version %u\n", fpgaversion);
+
+ return 0;
+}
+
+/* miscellaneous platform dependent initialisations */
+int misc_init_r(void)
+{
+ /* adjust flash start and offset to detected values */
+ gd->bd->bi_flashstart = flash_info[0].start[0];
+ gd->bd->bi_flashoffset = 0;
+
+ /* adjust mapping */
+ out_be32((void *)MPC5XXX_BOOTCS_START,
+ START_REG(gd->bd->bi_flashstart));
+ out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart));
+ out_be32((void *)MPC5XXX_BOOTCS_STOP,
+ STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+ out_be32((void *)MPC5XXX_CS0_STOP,
+ STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize));
+
+ return 0;
+}
+
+#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t * bd)
+{
+ ft_cpu_setup(blob, bd);
+}
+#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */
+
+#ifdef CONFIG_SPL_OS_BOOT
+/*
+ * A3M071 specific implementation of spl_start_uboot()
+ *
+ * RETURN
+ * 0 if booting into OS is selected (default)
+ * 1 if booting into U-Boot is selected
+ */
+int spl_start_uboot(void)
+{
+ char s[8];
+
+ env_init();
+ getenv_f("boot_os", s, sizeof(s));
+ if ((s != NULL) && (strcmp(s, "yes") == 0))
+ return 0;
+
+ return 1;
+}
+#endif
diff --git a/board/a3m071/mt46v16m16-75.h b/board/a3m071/mt46v16m16-75.h
new file mode 100644
index 0000000..e49e996
--- /dev/null
+++ b/board/a3m071/mt46v16m16-75.h
@@ -0,0 +1,32 @@
+/*
+ * (C) Copyright 2004
+ * Mark Jonas, Freescale Semiconductor, mark.jo...@motorola.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#define SDRAM_DDR /* is DDR */
+
+#if defined(CONFIG_MPC5200)
+/* Settings for XLB = 132 MHz */
+#define SDRAM_MODE 0x018D0000
+#define SDRAM_EMODE 0x40090000
+#define SDRAM_CONTROL 0x704f0f00
+#define SDRAM_CONFIG1 0x73722930
+#define SDRAM_CONFIG2 0x47770000
+#define SDRAM_TAPDELAY 0x10000000
+
+#else
+#error CONFIG_MPC5200 not defined
+#endif
diff --git a/boards.cfg b/boards.cfg
index fdb84ad..cbe9c27 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -431,6 +431,7 @@ mpc5121ads powerpc mpc512x
mpc5121ads freesca
mpc5121ads_rev2 powerpc mpc512x mpc5121ads
freescale - mpc5121ads:MPC5121ADS_REV2
cmi_mpc5xx powerpc mpc5xx cmi
PATI powerpc mpc5xx pati mpl
+a3m071 powerpc mpc5xxx a3m071
a4m072 powerpc mpc5xxx a4m072
BC3450 powerpc mpc5xxx bc3450
canmb powerpc mpc5xxx
diff --git a/include/configs/a3m071.h b/include/configs/a3m071.h
new file mode 100644
index 0000000..9cb457d
--- /dev/null
+++ b/include/configs/a3m071.h
@@ -0,0 +1,384 @@
+/*
+ * Copyright 2012 Stefan Roese <s...@denx.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC5200
+#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
+#define CONFIG_A3M071 /* ... on A3M071 board */
+#define CONFIG_MPC5200_DDR /* ... use DDR RAM */
+
+#define CONFIG_SYS_TEXT_BASE 0x01000000 /* boot low for 32 MiB
boards */
+
+#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */
+
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SYS_LOWBOOT /* Enable lowboot */
+
+/*
+ * Serial console configuration
+ */
+#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
+#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
+#define CONFIG_SYS_BAUDRATE_TABLE \
+ { 9600, 19200, 38400, 57600, 115200, 230400 }
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BSP
+#define CONFIG_CMD_CACHE
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_REGINFO
+#define CONFIG_CMD_SPL
+
+/*
+ * IPB Bus clocking configuration.
+ */
+#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz
speed */
+/* define for 66MHz speed - undef for 33MHz PCI clock speed */
+#undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
+
+/* pass open firmware flat tree */
+#define CONFIG_OF_LIBFDT
+#define CONFIG_OF_BOARD_SETUP
+
+/* maximum size of the flat tree (8K) */
+#define OF_FLAT_TREE_MAX_SIZE 8192
+
+#define OF_CPU "PowerPC,5200@0"
+#define OF_SOC "soc5200@f0000000"
+#define OF_TBCLK (bd->bi_busfreq / 4)
+#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
+
+/*
+ * I2C configuration
+ */
+#define CONFIG_HARD_I2C /* I2C with hardware
support */
+#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
+
+#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
+#define CONFIG_SYS_I2C_SLAVE 0x7F
+
+/*
+ * EEPROM configuration
+ */
+#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
+
+/*
+ * RTC configuration
+ */
+#define CONFIG_RTC_PCF8563
+#define CONFIG_SYS_I2C_RTC_ADDR 0x51
+
+/*
+ * NOR flash configuration
+ */
+#define CONFIG_SYS_FLASH_BASE 0xfc000000
+#define CONFIG_SYS_FLASH_SIZE 0x01000000
+#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE +
0x40000)
+
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_ERASE_TOUT 240000
+#define CONFIG_SYS_FLASH_WRITE_TOUT 500
+#define CONFIG_SYS_FLASH_LOCK_TOUT 5
+#define CONFIG_SYS_FLASH_UNLOCK_TOUT 10000
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+
+/*
+ * Environment settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_SIZE 0x10000
+#define CONFIG_ENV_SECT_SIZE 0x20000
+#define CONFIG_ENV_OVERWRITE
+
+/*
+ * Memory map
+ */
+#define CONFIG_SYS_MBAR 0xf0000000
+#define CONFIG_SYS_SDRAM_BASE 0x00000000
+#define CONFIG_SYS_DEFAULT_MBAR 0x80000000
+#define CONFIG_SYS_SRAM_BASE 0xF1000000
+#define CONFIG_SYS_SRAM_SIZE 0x200000
+#define CONFIG_SYS_LIME_BASE 0xE4000000
+#define CONFIG_SYS_LIME_SIZE 0x04000000
+
+/* Use SRAM until RAM will be available */
+#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
+#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
+
+
+#define CONFIG_SYS_GBL_DATA_SIZE 128
+#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
+ CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
+
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_MONITOR_LEN (256 << 10)
+#define CONFIG_SYS_MALLOC_LEN (1 << 20)
+#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
+
+/*
+ * Ethernet configuration
+ */
+#define CONFIG_MPC5xxx_FEC
+#define CONFIG_MPC5xxx_FEC_MII100
+#define CONFIG_PHY_ADDR 0x00
+
+/*
+ * GPIO configuration
+ */
+
+/*
+ * GPIO-config depends on failsave-level
+ * failsave 0 means just MPX-config, no digiboard, no fpga
+ * 1 means digiboard ok
+ * 2 means fpga ok
+ */
+
+/* for failsave-level 0 - full failsave */
+#define CONFIG_SYS_GPS_PORT_CONFIG 0x1005C005
+/* for failsave-level 1 - only digiboard ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_1 0x1005C005
+/* for failsave-level 2 - all ok */
+#define CONFIG_SYS_GPS_PORT_CONFIG_2 0x1005C005
+
+/*
+ * Configuration matrix
+ * MSB LSB
+ * failsave 0 0x1005C005 00010000000001011100000000000101 ( full failsave )
+ * failsave 1 0x1005C005 00010000000001011100000000000101 ( digib.-ver ok )
+ * failsave 2 0x1005C005 00010000000001011100000000000101 ( all ok )
+ * || ||| || | ||| | | | |
+ * || ||| || | ||| | | | | bit rev name
+ * ++-+++-++--+---+++-+---+---+---+- 0 31 CS1
+ * +-+++-++--+---+++-+---+---+---+- 1 30 LPTZ
+ * ||| || | ||| | | | | 2 29 ALTs
+ * +++-++--+---+++-+---+---+---+- 3 28 ALTs
+ * ++-++--+---+++-+---+---+---+- 4 27 CS7
+ * +-++--+---+++-+---+---+---+- 5 26 CS6
+ * || | ||| | | | | 6 25 ATA
+ * ++--+---+++-+---+---+---+- 7 24 ATA
+ * +--+---+++-+---+---+---+- 8 23 IR_USB_CLK
+ * | ||| | | | | 9 22 IRDA
+ * | ||| | | | | 10 21 IRDA
+ * +---+++-+---+---+---+- 11 20 IRDA
+ * ||| | | | | 12 19 Ether
+ * ||| | | | | 13 18 Ether
+ * ||| | | | | 14 17 Ether
+ * +++-+---+---+---+- 15 16 Ether
+ * ++-+---+---+---+- 16 15 PCI_DIS
+ * +-+---+---+---+- 17 14 USB_SE
+ * | | | | 18 13 USB
+ * +---+---+---+- 19 12 USB
+ * | | | 20 11 PSC3
+ * | | | 21 10 PSC3
+ * | | | 22 9 PSC3
+ * +---+---+- 23 8 PSC3
+ * | | 24 7 -
+ * | | 25 6 PSC2
+ * | | 26 5 PSC2
+ * +---+- 27 4 PSC2
+ * | 28 3 -
+ * | 29 2 PSC1
+ * | 30 1 PSC1
+ * +- 31 0 PSC1
+ */
+
+
+/*
+ * Miscellaneous configurable options
+ */
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_SYS_PROMPT "=> "
+
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
+
+#if defined(CONFIG_CMD_KGDB)
+#define CONFIG_SYS_CBSIZE 1024
+#else
+#define CONFIG_SYS_CBSIZE 256
+#endif
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
+#define CONFIG_SYS_MAXARGS 16
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#define CONFIG_SYS_MEMTEST_START 0x00100000
+#define CONFIG_SYS_MEMTEST_END 0x00f00000
+
+#define CONFIG_SYS_LOAD_ADDR 0x00100000
+
+#define CONFIG_SYS_HZ 1000
+#define CONFIG_LOOPW
+#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
+
+/*
+ * Various low-level settings
+ */
+#define CONFIG_SYS_HID0_INIT (HID0_ICE | HID0_ICFI)
+#define CONFIG_SYS_HID0_FINAL HID0_ICE
+
+#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
+#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
+#define CONFIG_SYS_CS1_START CONFIG_SYS_SRAM_BASE
+#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_SRAM_SIZE
+#define CONFIG_SYS_CS2_START 0xe0000000
+#define CONFIG_SYS_CS2_SIZE 0x00100000
+
+/* FPGA slave io (512kiB) - see ticket #66 */
+#define CONFIG_SYS_CS3_START 0xE9000000
+#define CONFIG_SYS_CS3_SIZE 0x00080000
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
+#define CONFIG_SYS_CS3_CFG 0x0032B900
+
+/* Diagnosis Interface - see ticket #63 */
+#define CONFIG_SYS_CS4_START 0xEA000000
+#define CONFIG_SYS_CS4_SIZE 0x00000001
+/* 00000000 00000010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0002B900 */
+#define CONFIG_SYS_CS4_CFG 0x0002B900
+
+/* FPGA master io (64kiB) - see ticket #66 */
+#define CONFIG_SYS_CS5_START 0xE8000000
+#define CONFIG_SYS_CS5_SIZE 0x00010000
+/* 00000000 00110010 1 0 1 1 10 01 00 00 0 0 0 0 = 0x0032B900 */
+#define CONFIG_SYS_CS5_CFG 0x0032B900
+
+#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* for pci_clk = 66 MHz */
+#define CONFIG_SYS_BOOTCS_CFG 0x0006F900
+#define CONFIG_SYS_CS1_CFG 0x0004FB00
+#define CONFIG_SYS_CS2_CFG 0x0006F90C
+#else /* for pci_clk = 33 MHz */
+#define CONFIG_SYS_BOOTCS_CFG 0x0002F900
+#define CONFIG_SYS_CS1_CFG 0x0001FB00
+#define CONFIG_SYS_CS2_CFG 0x0002F90C
+#endif
+
+#define CONFIG_SYS_CS_BURST 0x00000000
+/* set DC for FPGA CS5 and CS3 to 0 - see ticket #66 */
+/* R 7 R 6 R 5 R 4 R 3 R 2 R 1 R 0 */
+/* 00 11 00 11 00 00 00 11 00 00 00 00 00 00 00 00 */
+#define CONFIG_SYS_CS_DEADCYCLE 0x33030000
+
+#define CONFIG_SYS_RESET_ADDRESS 0xff000000
+
+/*
+ * Environment Configuration
+ */
+
+#define CONFIG_BOOTDELAY 0 /* -1 disables auto-boot */
+#undef CONFIG_BOOTARGS
+#define CONFIG_ZERO_BOOTDELAY_CHECK
+
+#define CONFIG_PREBOOT "echo;" \
+ "echo Type \"run flash_mtd\" to boot from flash with mtd filesystem;" \
+ "echo Type \"run net_nfs\" to boot from tftp with nfs filesystem;" \
+ "echo"
+
+#undef CONFIG_BOOTARGS
+
+#define CONFIG_SYS_OS_BASE 0xfc080000
+#define CONFIG_SYS_FDT_BASE 0xfc060000
+
+#define xstr(s) str(s)
+#define str(s) #s
+
+#define CONFIG_EXTRA_ENV_SETTINGS
\
+ "netdev=eth0\0" \
+ "verify=no\0" \
+ "consoledev=ttyPSC0\0" \
+ "nfsargs=setenv bootargs root=/dev/nfs rw " \
+ "nfsroot=${serverip}:${rootpath}\0" \
+ "ramargs=setenv bootargs root=/dev/ram rw\0" \
+ "mtdargs=setenv bootargs root=/dev/mtdblock4 rw rootfstype=jffs2\0"\
+ "addip=setenv bootargs ${bootargs} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
+ ":${hostname}:${netdev}:off panic=1\0" \
+ "addtty=setenv bootargs ${bootargs}
console=${consoledev},${baudrate}\0"\
+ "flash_nfs=run nfsargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdtaddr}\0" \
+ "flash_mtd=run mtdargs addip addtty;" \
+ "bootm ${kernel_addr} - ${fdtaddr}\0" \
+ "flash_self=run ramargs addip addtty;" \
+ "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0" \
+ "net_nfs=sleep 2; tftp ${loadaddr} ${bootfile}; tftp c00000
${fdtfile};"\
+ "run nfsargs addip addtty;" \
+ "bootm ${loadaddr} - c00000\0" \
+ "load=tftp ${loadaddr} u-boot.bin\0" \
+ "update=protect off fc000000 fc03ffff; " \
+ "era fc000000 fc03ffff; cp.b ${loadaddr} fc000000 40000\0"\
+ "upd=run load;run update\0" \
+ "fdtaddr=" xstr(CONFIG_SYS_FDT_BASE) "\0" \
+ "fdtfile=dtbFile\0" \
+ "kernel_addr=" xstr(CONFIG_SYS_OS_BASE) "\0" \
+ ""
+
+#define CONFIG_BOOTCOMMAND "run flash_mtd"
+
+/*
+ * SPL related defines
+ */
+#define CONFIG_SPL
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_NOR_SUPPORT
+#define CONFIG_SPL_TEXT_BASE 0xfc000000
+#define CONFIG_SPL_START_S_PATH "arch/powerpc/cpu/mpc5xxx"
+#define CONFIG_SPL_LDSCRIPT "arch/powerpc/cpu/mpc5xxx/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
+#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
+
+/* Place BSS for SPL near end of SDRAM */
+#define CONFIG_SPL_BSS_START_ADDR ((128 - 1) << 20)
+#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
+
+#define CONFIG_SPL_OS_BOOT
+/* Place patched DT blob (fdt) at this address */
+#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
+
+#define CONFIG_SYS_SPL_LEN 32768
+#define CONFIG_SYS_PAD_TO 0xfc008000
+
+/* Settings for real U-Boot to be loaded from NOR flash */
+#define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \
+ CONFIG_SYS_SPL_LEN)
+#define CONFIG_SYS_UBOOT_START (CONFIG_SYS_TEXT_BASE + 0x100)
+
+#endif /* __CONFIG_H */
--
1.7.12
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