This build is stripped down. It boots to the command prompt.
GPIO is the only peripheral supported. Others TBD.
Signed-off-by: Tom Warren <twar...@nvidia.com>
---
board/nvidia/{whistler => cardhu}/Makefile | 4 ++
.../cpu/cpu.c => board/nvidia/cardhu/cardhu.c | 8 ++--
boards.cfg | 1 +
.../gp_padctrl.h => include/configs/cardhu.h | 37 +++++++++----
.../configs/{tegra20-common.h => tegra30-common.h} | 54 +++++---------------
5 files changed, 48 insertions(+), 56 deletions(-)
copy board/nvidia/{whistler => cardhu}/Makefile (94%)
copy arch/microblaze/cpu/cpu.c => board/nvidia/cardhu/cardhu.c (88%)
copy arch/arm/include/asm/arch-tegra/gp_padctrl.h => include/configs/cardhu.h
(55%)
copy include/configs/{tegra20-common.h => tegra30-common.h} (77%)
diff --git a/board/nvidia/whistler/Makefile b/board/nvidia/cardhu/Makefile
similarity index 94%
copy from board/nvidia/whistler/Makefile
copy to board/nvidia/cardhu/Makefile
index 913f1ce..a910577 100644
--- a/board/nvidia/whistler/Makefile
+++ b/board/nvidia/cardhu/Makefile
@@ -24,6 +24,10 @@
include $(TOPDIR)/config.mk
+ifneq ($(OBJTREE),$(SRCTREE))
+$(shell mkdir -p $(obj)../common)
+endif
+
LIB = $(obj)lib$(BOARD).o
COBJS := $(BOARD).o
diff --git a/arch/microblaze/cpu/cpu.c b/board/nvidia/cardhu/cardhu.c
similarity index 88%
copy from arch/microblaze/cpu/cpu.c
copy to board/nvidia/cardhu/cardhu.c
index 4d2b270..69b89db 100644
--- a/arch/microblaze/cpu/cpu.c
+++ b/board/nvidia/cardhu/cardhu.c
@@ -1,7 +1,6 @@
/*
- * (C) Copyright 2004 Atmark Techno, Inc.
- *
- * Yasushi SHOJI <ya...@atmark-techno.com>
+ * (C) Copyright 2010-2012
+ * NVIDIA Corporation <www.nvidia.com>
*
* See file CREDITS for list of people who contributed to this
* project.
@@ -22,4 +21,5 @@
* MA 02111-1307 USA
*/
-/* EMPTY FILE */
+#include <common.h>
+
diff --git a/boards.cfg b/boards.cfg
index 4ae6656..7fb17ca 100644
--- a/boards.cfg
+++ b/boards.cfg
@@ -270,6 +270,7 @@ harmony arm armv7:arm720t
harmony nvidia
seaboard arm armv7:arm720t seaboard
nvidia tegra20
ventana arm armv7:arm720t ventana
nvidia tegra20
whistler arm armv7:arm720t whistler
nvidia tegra20
+cardhu arm armv7:arm720t cardhu
nvidia tegra30
u8500_href arm armv7 u8500
st-ericsson u8500
snowball arm armv7 snowball
st-ericsson u8500
actux1_4_16 arm ixp actux1 -
- actux1:FLASH2X2
diff --git a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
b/include/configs/cardhu.h
similarity index 55%
copy from arch/arm/include/asm/arch-tegra/gp_padctrl.h
copy to include/configs/cardhu.h
index d347e97..bfadbff 100644
--- a/arch/arm/include/asm/arch-tegra/gp_padctrl.h
+++ b/include/configs/cardhu.h
@@ -21,17 +21,32 @@
* MA 02111-1307 USA
*/
-#ifndef _TEGRA_GP_PADCTRL_H_
-#define _TEGRA_GP_PADCTRL_H_
+#ifndef __CONFIG_H
+#define __CONFIG_H
-/* bit fields definitions for APB_MISC_GP_HIDREV register */
-#define HIDREV_CHIPID_SHIFT 8
-#define HIDREV_CHIPID_MASK (0xff << HIDREV_CHIPID_SHIFT)
-#define HIDREV_MAJORPREV_SHIFT 4
-#define HIDREV_MAJORPREV_MASK (0xf << HIDREV_MAJORPREV_SHIFT)
+#include <asm/sizes.h>
-/* CHIPID field returned from APB_MISC_GP_HIDREV register */
-#define CHIPID_TEGRA20 0x20
-#define CHIPID_TEGRA30 0x30
+#include "tegra30-common.h"
-#endif /* _TEGRA_GP_PADCTRL_H_ */
+/* Enable fdt support for Cardhu. Flash the image in u-boot-dtb.bin */
+#define CONFIG_DEFAULT_DEVICE_TREE tegra30-cardhu
+#define CONFIG_OF_CONTROL
+#define CONFIG_OF_SEPARATE
+
+/* High-level configuration options */
+#define V_PROMPT "Tegra30 (Cardhu) # "
+#define CONFIG_TEGRA_BOARD_STRING "NVIDIA Cardhu"
+
+/* Board-specific serial config */
+#define CONFIG_SERIAL_MULTI
+#define CONFIG_TEGRA_ENABLE_UARTA
+#define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
+
+#define CONFIG_MACH_TYPE MACH_TYPE_CARDHU
+
+#define CONFIG_BOARD_EARLY_INIT_F
+#define CONFIG_ENV_IS_NOWHERE
+
+#include "tegra-common-post.h"
+
+#endif /* __CONFIG_H */
diff --git a/include/configs/tegra20-common.h b/include/configs/tegra30-common.h
similarity index 77%
copy from include/configs/tegra20-common.h
copy to include/configs/tegra30-common.h
index 744dc59..d281b61 100644
--- a/include/configs/tegra20-common.h
+++ b/include/configs/tegra30-common.h
@@ -21,8 +21,8 @@
* MA 02111-1307 USA
*/
-#ifndef __TEGRA20_COMMON_H
-#define __TEGRA20_COMMON_H
+#ifndef __TEGRA30_COMMON_H
+#define __TEGRA30_COMMON_H
#include <asm/sizes.h>
/*
@@ -37,7 +37,7 @@
* High Level Configuration Options
*/
#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
-#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
+#define CONFIG_TEGRA30 /* in a NVidia Tegra30 core */
#define CONFIG_TEGRA /* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
@@ -54,15 +54,6 @@
#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
-#ifdef CONFIG_TEGRA_LP0
-#define TEGRA_LP0_ADDR 0x1C406000
-#define TEGRA_LP0_SIZE 0x2000
-#define TEGRA_LP0_VEC \
- "lp0_vec=" QUOTE(TEGRA_LP0_SIZE) "@" QUOTE(TEGRA_LP0_ADDR) " "
-#else
-#define TEGRA_LP0_VEC
-#endif
-
/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE 0x2000 /* Total Size
Environment */
@@ -95,26 +86,9 @@
/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE 115200
-#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
- 115200}
-
-/*
- * This parameter affects a TXFILLTUNING field that controls how much data is
- * sent to the latency fifo before it is sent to the wire. Without this
- * parameter, the default (2) causes occasional Data Buffer Errors in OUT
- * packets depending on the buffer address and size.
- */
-#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
-#define CONFIG_EHCI_IS_TDI
-#define CONFIG_EHCI_DCACHE
-
-/* Total I2C ports on Tegra20 */
-#define TEGRA_I2C_NUM_CONTROLLERS 4
/* include default commands */
#include <config_cmd_default.h>
-#define CONFIG_PARTITION_UUIDS
-#define CONFIG_CMD_PART
/* remove unused commands */
#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
@@ -138,7 +112,7 @@
"stdout=serial\0" \
"stderr=serial\0"
-#define CONFIG_LOADADDR 0x408000 /* def. location for
kernel */
+#define CONFIG_LOADADDR 0x80408000 /* def. location for
kernel */
#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
/*
@@ -162,10 +136,10 @@
#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
-#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
+#define CONFIG_SYS_LOAD_ADDR (0x80A00800) /* default */
#define CONFIG_SYS_HZ 1000
-#define CONFIG_STACKBASE 0x2800000 /* 40MB */
+#define CONFIG_STACKBASE 0x82800000 /* 40MB */
/*-----------------------------------------------------------------------
* Physical Memory Map
@@ -174,7 +148,7 @@
#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
-#define CONFIG_SYS_TEXT_BASE 0x0010c000
+#define CONFIG_SYS_TEXT_BASE 0x8010e000
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
@@ -191,18 +165,16 @@
/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_NAND_SIMPLE
-#define CONFIG_SPL_TEXT_BASE 0x00108000
-#define CONFIG_SPL_MAX_SIZE 0x00004000
-#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
+#define CONFIG_SPL_TEXT_BASE 0x80108000
+#define CONFIG_SPL_MAX_SIZE 0x00006000
+#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
-#define CONFIG_SPL_STACK 0x000ffffc
+#define CONFIG_SPL_STACK 0x800ffffc
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
-
-#define CONFIG_SYS_NAND_SELF_INIT
+#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra30/u-boot-spl.lds"
-#endif /* __TEGRA20_COMMON_H */
+#endif /* __TEGRA30_COMMON_H */
--
1.7.0.4
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