Hi Simon, No comment on the patch itself except for one general question:
On Mon, 8 Oct 2012 14:42:29 -0700, Simon Glass <s...@chromium.org> wrote: > Add support for adjusting the cachability of an L1 section by updating > the MMU. The mmu_set_region_dcache() function allows drivers to make > these changes after the MMU is set up. Can you just reformulate this a bit? "L1" is not necessary about cache (there can be for instance TCM, frequently (if not correctly) called L1 RAM where I work, for the obvious reason that they are accessed at the same level/layer as the L1 cache. Also, off, writethrough and copyback are "cache behaviors" in ARM parlance, not "cachability". Therefore I would prefer something like "Add support for adjusting the L1 cache behavior by updating the MMU configuration. The mmu_set_region_dcache_behavior() function allows drivers to make these changes after the MMU is set up." (note the suggestion includes slightly renaming the function) Thanks in advance for considering this suggestion. Amicalement, -- Albert. _______________________________________________ U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot