xf86-video-intel commit 736b89504a32239a0c7dfb5961c1b8292dd744bd
Author: Chris Wilson <ch...@chris-wilson.co.uk>
Date: Sun Dec 30 10:32:18 2012 +0000
uxa: Align surface allocations to even tile rows
Align surface sizes to an even number of tile rows to cater for sampler
prefetch. If we read beyond the last page we may catch the PTE in a
state of flux and trigger a GPU hang. Also detected by enabling invalid
PTE access checking.
References: https://bugs.freedesktop.org/show_bug.cgi?id=56916
References: https://bugs.freedesktop.org/show_bug.cgi?id=55984
Signed-off-by: Chris Wilson <ch...@chris-wilson.co.uk
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https://bugs.launchpad.net/bugs/1081009
Title:
[arrandale] GPU lockup IPEHR: 0x02000022
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