Michael Schnell wrote: > >I would like to have an SMP uClinux running on the multilple NIOS II > >processors architecture (with or without cache coherence). > You might want to discuss this on the NIOS2 uCLinux mailing list: > nios2-...@sopc.et.ntust.edu.tw . > > Did you already solve the appropriate hardware issues ? > > I suppose you _can_ add multiples NIOS processors to the Avalon bus > using the SOPC-Builder. > > But for SMP they would need to access a common memory and here you need > to take care of cache consistence. AFAIK, this is not supported at all > with the current NIOS Altera ip Core. So you would need to switch off > the data cache completely, resulting in a very slow system. Maybe on top > of this, you can do a cache design of your own in HDLC: either a common > stack for both processors (quite slow due to the need for scheduling the > requests) or a stack for either of them with additional hardware to > invalidate the cache lines that are written by the other processor and > to force writing of the cache lines read by the other processing <or > similar>.
You can tell Linux to explicitly flush cache lines, so that you don't need consistency in hardware. You only need cache line flushing instructions, which is simpler hardware. You need those instructions anyway if you have peripherals doing DMA to main memory, so you might not need any changes to the hardware cache. -- Jamie _______________________________________________ uClinux-dev mailing list uClinux-dev@uclinux.org http://mailman.uclinux.org/mailman/listinfo/uclinux-dev This message was resent by uclinux-dev@uclinux.org To unsubscribe see: http://mailman.uclinux.org/mailman/options/uclinux-dev
