On Thu, Jun 03, 2010 at 09:49:40AM +0200, angelo wrote:
> i have almost the sending part of the driver up and running, with some
> small changes,
> but as you said, it is written to work with little endian cpu.
>
> It is not a problem of "bit" ordering, as in your diagram below.
> Endianness here mean "byte-ordering" of the data in the memory, done
> from the cpu.
>
> A byte cross-wiring, without any bit-swapping, should solve the issue,
> to allow the driver to be used as is:
>
> D0:D7 cpu wired -> D24:D31 dm9000
> D8:D15 cpu wired -> D16:D23 dm9000
> D16:D23 cpu wired -> D8:D15 dm9000
> D24:D31 cpu wired -> D0:D7 dm9000
>
> I probably should try it in a next version of the board.
>
> What i do is to use "writel" instade of "writeb", and i have magically
> the byte out on dm9000 D0:D7. Then, DMA writings are configured through
> a dm9000 bootstrap pin as 32bit. Here the byte swapping is required, and
> i use le32_to_cpu() kernel function.
>
> What still not work is the receiving part, and probably i am not
> understanding very well the
> dm9000 resource structure, here it is finally:
>
> #define INT_IRQ7 31
>
> static struct resource dm9000_resources[] = {
> /* physical address of the address register (CMD [A2] to 0)*/
> [0] = {
> .start = MCF5307_CS1,
> .end = MCF5307_CS1,
> .flags = IORESOURCE_MEM,
> },
> /* physical address of the data register (CMD [A2] to 1)*/
> [1] = {
> .start = MCF5307_CS1 + 0x4,
> .end = MCF5307_CS1 + 0x4 + 03,
> .flags = IORESOURCE_MEM,
> },
> /* IRQ line the device's interrupt pin is connected to */
> [2] = {
> .start = INT_IRQ7,
> .end = INT_IRQ7,
> .flags = (IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE),
> },
> };
>
>
> Irq vector for HW IRQ7 should be @ offset 31.
> But who write there int the table the address of the dm9000 routine ? Is
> it done automatically at dm9000 driver startup ?
>
> any help is appreciated.
No idea on the IRQ bit. I am sure you will figure it out though.
--
Len Sorensen
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