Re: [uClinux-dev] [RFC/PATCH] m68knommu: Add clk definitions for m532x.

Greg Ungerer Sun, 17 Jun 2012 22:06:57 -0700

Hi Steven,

On 17/06/12 17:41, Steven King wrote:

The 532x has individually controllable clocks for it peripherals.  Add clk
definitions for these and add default initialization of either enabled or
disabled.


Signed-off-by: Steven King<sfk...@fdwdc.com>
---
  arch/m68k/include/asm/m532xsim.h    |   14 ++++
  arch/m68k/platform/coldfire/m532x.c |  139 ++++++++++++++++++++++++++++++++++-
  2 files changed, 152 insertions(+), 1 deletion(-)

diff --git a/arch/m68k/include/asm/m532xsim.h b/arch/m68k/include/asm/m532xsim.h
index 8d86020..5ca7b29 100644
--- a/arch/m68k/include/asm/m532xsim.h
+++ b/arch/m68k/include/asm/m532xsim.h
@@ -138,6 +138,20 @@
  #define       MCF_RCR_SWRESET         0x80            /* Software reset bit */
  #define       MCF_RCR_FRCSTOUT        0x40            /* Force external reset 
*/

+
+/*
+ * Power Management
+ */
+#define MCFPM_WCR              0xfc040013
+#define MCFPM_PPMSR0           0xfc04002c
+#define MCFPM_PPMCR0           0xfc04002d
+#define MCFPM_PPMSR1           0xfc04002e
+#define MCFPM_PPMCR1           0xfc04002f
+#define MCFPM_PPMHR0           0xfc040030
+#define MCFPM_PPMLR0           0xfc040034
+#define MCFPM_PPMHR1           0xfc040038
+#define MCFPM_LPCR             0xec090007


Do these definitions have anything to do the the clocks?
I don't see them used anywhere in this patch?

This applies to the m520x clock patch to I think.

Regards
Greg

  /*********************************************************************
   *
   * Inter-IC (I2C) Module
diff --git a/arch/m68k/platform/coldfire/m532x.c 
b/arch/m68k/platform/coldfire/m532x.c
index 21d6cb1..97107a8 100644
--- a/arch/m68k/platform/coldfire/m532x.c
+++ b/arch/m68k/platform/coldfire/m532x.c
@@ -27,6 +27,143 @@
  #include<asm/mcfuart.h>
  #include<asm/mcfdma.h>
  #include<asm/mcfwdebug.h>
+#include<asm/mcfclk.h>
+
+/***************************************************************************/
+
+DEFINE_CLK(0, "flexbus", 2, MCF_CLK);
+DEFINE_CLK(0, "mcfcan.0", 8, MCF_CLK);
+DEFINE_CLK(0, "fec.0", 12, MCF_CLK);
+DEFINE_CLK(0, "edma", 17, MCF_CLK);
+DEFINE_CLK(0, "intc.0", 18, MCF_CLK);
+DEFINE_CLK(0, "intc.1", 19, MCF_CLK);
+DEFINE_CLK(0, "iack.0", 21, MCF_CLK);
+DEFINE_CLK(0, "mcfi2c.0", 22, MCF_CLK);
+DEFINE_CLK(0, "mcfqspi.0", 23, MCF_CLK);
+DEFINE_CLK(0, "mcfuart.0", 24, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.1", 25, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfuart.2", 26, MCF_BUSCLK);
+DEFINE_CLK(0, "mcftmr.0", 28, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.1", 29, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.2", 30, MCF_CLK);
+DEFINE_CLK(0, "mcftmr.3", 31, MCF_CLK);
+
+DEFINE_CLK(0, "mcfpit.0", 32, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.1", 33, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.2", 34, MCF_CLK);
+DEFINE_CLK(0, "mcfpit.3", 35, MCF_CLK);
+DEFINE_CLK(0, "mcfpwm.0", 36, MCF_CLK);
+DEFINE_CLK(0, "mcfeport.0", 37, MCF_CLK);
+DEFINE_CLK(0, "mcfwdt.0", 38, MCF_CLK);
+DEFINE_CLK(0, "sys.0", 40, MCF_BUSCLK);
+DEFINE_CLK(0, "gpio.0", 41, MCF_BUSCLK);
+DEFINE_CLK(0, "mcfrtc.0", 42, MCF_CLK);
+DEFINE_CLK(0, "mcflcd.0", 43, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-otg.0", 44, MCF_CLK);
+DEFINE_CLK(0, "mcfusb-host.0", 45, MCF_CLK);
+DEFINE_CLK(0, "sdram.0", 46, MCF_CLK);
+DEFINE_CLK(0, "ssi.0", 47, MCF_CLK);
+DEFINE_CLK(0, "pll.0", 48, MCF_CLK);
+
+DEFINE_CLK(1, "mdha.0", 32, MCF_CLK);
+DEFINE_CLK(1, "skha.0", 33, MCF_CLK);
+DEFINE_CLK(1, "rng.0", 34, MCF_CLK);
+
+struct clk *mcf_clks[] = {
+       &__clk_0_2, /* flexbus */
+       &__clk_0_8, /* mcfcan.0 */
+       &__clk_0_12,        /* fec.0 */
+       &__clk_0_17,        /* edma */
+       &__clk_0_18,        /* intc.0 */
+       &__clk_0_19,        /* intc.1 */
+       &__clk_0_21,        /* iack.0 */
+       &__clk_0_22,        /* mcfi2c.0 */
+       &__clk_0_23,        /* mcfqspi.0 */
+       &__clk_0_24,        /* mcfuart.0 */
+       &__clk_0_25,        /* mcfuart.1 */
+       &__clk_0_26,        /* mcfuart.2 */
+       &__clk_0_28,        /* mcftmr.0 */
+       &__clk_0_29,        /* mcftmr.1 */
+       &__clk_0_30,        /* mcftmr.2 */
+       &__clk_0_31,        /* mcftmr.3 */
+
+       &__clk_0_32,        /* mcfpit.0 */
+       &__clk_0_33,        /* mcfpit.1 */
+       &__clk_0_34,        /* mcfpit.2 */
+       &__clk_0_35,        /* mcfpit.3 */
+       &__clk_0_36,        /* mcfpwm.0 */
+       &__clk_0_37,        /* mcfeport.0 */
+       &__clk_0_38,        /* mcfwdt.0 */
+       &__clk_0_40,        /* sys.0 */
+       &__clk_0_41,        /* gpio.0 */
+       &__clk_0_42,        /* mcfrtc.0 */
+       &__clk_0_43,        /* mcflcd.0 */
+       &__clk_0_44,        /* mcfusb-otg.0 */
+       &__clk_0_45,        /* mcfusb-host.0 */
+       &__clk_0_46,        /* sdram.0 */
+       &__clk_0_47,        /* ssi.0 */
+       &__clk_0_48,        /* pll.0 */
+
+       &__clk_1_32,        /* mdha.0 */
+       &__clk_1_33,        /* skha.0 */
+       &__clk_1_34,        /* rng.0 */
+       NULL,
+};
+
+static struct clk * const enable_clks[] __initconst = {
+       &__clk_0_2, /* flexbus */
+       &__clk_0_18,        /* intc.0 */
+       &__clk_0_19,        /* intc.1 */
+       &__clk_0_21,        /* iack.0 */
+       &__clk_0_24,        /* mcfuart.0 */
+       &__clk_0_25,        /* mcfuart.1 */
+       &__clk_0_26,        /* mcfuart.2 */
+
+       &__clk_0_32,        /* mcfpit.0 */
+       &__clk_0_33,        /* mcfpit.1 */
+       &__clk_0_37,        /* mcfeport.0 */
+       &__clk_0_40,        /* sys.0 */
+       &__clk_0_41,        /* gpio.0 */
+       &__clk_0_46,        /* sdram.0 */
+       &__clk_0_48,        /* pll.0 */
+};
+
+static struct clk * const disable_clks[] __initconst = {
+       &__clk_0_8, /* mcfcan.0 */
+       &__clk_0_12,        /* fec.0 */
+       &__clk_0_17,        /* edma */
+       &__clk_0_22,        /* mcfi2c.0 */
+       &__clk_0_23,        /* mcfqspi.0 */
+       &__clk_0_28,        /* mcftmr.0 */
+       &__clk_0_29,        /* mcftmr.1 */
+       &__clk_0_30,        /* mcftmr.2 */
+       &__clk_0_31,        /* mcftmr.3 */
+       &__clk_0_34,        /* mcfpit.2 */
+       &__clk_0_35,        /* mcfpit.3 */
+       &__clk_0_36,        /* mcfpwm.0 */
+       &__clk_0_38,        /* mcfwdt.0 */
+       &__clk_0_42,        /* mcfrtc.0 */
+       &__clk_0_43,        /* mcflcd.0 */
+       &__clk_0_44,        /* mcfusb-otg.0 */
+       &__clk_0_45,        /* mcfusb-host.0 */
+       &__clk_0_47,        /* ssi.0 */
+       &__clk_1_32,        /* mdha.0 */
+       &__clk_1_33,        /* skha.0 */
+       &__clk_1_34,        /* rng.0 */
+};
+
+
+static void __init m532x_clk_init(void)
+{
+       unsigned i;
+
+       /* make sure these clocks are enabled */
+       for (i = 0; i<  ARRAY_SIZE(enable_clks); ++i)
+               __clk_init_enabled(enable_clks[i]);
+       /* make sure these clocks are disabled */
+       for (i = 0; i<  ARRAY_SIZE(disable_clks); ++i)
+               __clk_init_disabled(disable_clks[i]);
+}

  /***************************************************************************/

@@ -73,7 +210,7 @@ void __init config_BSP(char *commandp, int size)
                memset(commandp, 0, size);
        }
  #endif
-
+       m532x_clk_init();
        mach_sched_init = hw_timer_init;
        m532x_uarts_init();
        m532x_fec_init();



--
------------------------------------------------------------------------
Greg Ungerer  --  Principal Engineer        EMAIL:     g...@snapgear.com
SnapGear Group, McAfee                      PHONE:       +61 7 3435 2888
8 Gardner Close                             FAX:         +61 7 3217 5323
Milton, QLD, 4064, Australia                WEB: http://www.SnapGear.com
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Re: [uClinux-dev] [RFC/PATCH] m68knommu: Add clk definitions for m532x.

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