> What about two Xilinx FPGA chips I have sent config files for - I > cannot see them in current source tree? Were they added? If now how > can I add them?
I'd recommend not to add such config files for FPGA/CPLD chips anymore. Why? For two reasons: First, with native BSDL support in UrJTAG it's not required anymore to have re-formatted config files; the BSDLs are freely available from Xilinx (and Altera, Lattice, etc). Secondly, they're cumbersome to set up and maintain correctly. All package variants of a certain chip carry the same IDCODE, thus there's no way for UrJTAG to determine which config file to load automatically. There have been exhaustive approaches to cover this (data/altera/ep2c8 is a good example) in the past. But that's not worth the effort anymore when BSDL files can be used natively in UrJTAG, IMHO. Best regards Arnim ------------------------------------------------------------------------------ Download Intel® Parallel Studio Eval Try the new software tools for yourself. Speed compiling, find bugs proactively, and fine-tune applications for parallel performance. See why Intel Parallel Studio got high marks during beta. http://p.sf.net/sfu/intel-sw-dev _______________________________________________ UrJTAG-development mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/urjtag-development
