Dear Gaston,

> Stapl tested ok with a ".jam" file generated for a Altera EPF10K20 Fpga.
> This is an old device, so the Quartus version is also old (7.2), and the
> Stapl version generated is 2.0. The real challenge will be make a test
> with a newer Fpga, using the latest version of Quartus, but I don't have
> any.

Thank you very much for your tests on different hardware. Meanwhile, I 
have tested the UrJTAG & stapl on the same Actel ProASIC3E A3PE1500 with 
Altera USB Blaster and FT2232H (USB2.0). With the FT2232H, whole 
programming (FLASH) and verification took 1m34s, which seems to be quite 
good (I must later check the time of original Window$ FlashPro).

We have discovered a severe bug: there is a very naive function 
delay_loop, which tries to implement delays using empty for-cycle... (and 
to callibrate them). After change to usleep(), it works great.

/*
There are/were more such things, such as a standalone memory allocator, 
which should not be there in future -- these functions should be 
implemented on an embedded computer in its particular system stub, not in 
the STAPL player, of course. The memory allocator cooperating with e.g. 
newlib can be written as an _sbrk stub within <5 lines of code...

The same apply with delays on an embedded platform. I really think the 
open-source force would revive the player itself.
*/

> I suppose that changes introduces by Actel and recents changes in the
> Altera player are unrelated, so a simple merge could work.

The code submitted by Michael is based on both Altera code and later 
Actel's modification. The two branches are being slightly updated by A.&A. 
separately. The version submitted should be the best union of the 
functionality offered to date.

I strongly hope, that some meaningful continuation will be possible after 
licensing will be made clear.


Again, many thanks for testing & good luck!
Marek

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