On Thu, Mar 17, 2011 at 9:33 AM, David George <[email protected]> wrote: > I am currently using urjtag to debug a PPC440 processor. To do this I > need to be able to manipulate the processor HALT signal from an FTDI > chip. I would guess that the best place for this would be in the POD > infrastructure. Is this correct?
try "pod reset=0" and connect sRST to the target's reset signal, this will allow you to access the DAP. If you think of "HALT" as in OpenOCD - this is not the level you want - you need to operate on the DAP. Best regards, Tomek -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info ------------------------------------------------------------------------------ Colocation vs. Managed Hosting A question and answer guide to determining the best fit for your organization - today and in the future. http://p.sf.net/sfu/internap-sfd2d _______________________________________________ UrJTAG-development mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/urjtag-development
