On Monday, August 29, 2011 17:22:16 Jie Zhang wrote: > On Mon, Aug 29, 2011 at 4:13 PM, Mike Frysinger <[email protected]> wrote: > > On Monday, August 29, 2011 15:54:35 Jie Zhang wrote: > >> On Mon, Aug 29, 2011 at 3:22 PM, Mike Frysinger <[email protected]> wrote: > >> > On Monday, August 29, 2011 10:38:17 Jie Zhang wrote: > >> >> I have committed this patch to add BF527 SDP board bus support. I did > >> >> the test by detectflash, but did not try flashmem. > >> > > >> > this already works with the bf52x bus. simply pass HWAIT=PG0 when > >> > initializing it. i tested that with detecting, reading, and writing > >> > flash when i implemented it. > >> > >> I was wondering what's the use of HWAIT. Now I see. Thank you! > >> > >> But the problem is it's not easy for user to know they can use this > >> parameter for BF527 SDP board. As I said before, we should allow user > >> to add board names to initbus explicitly. Otherwise, people will keep > >> asking if board FOO is supported or not. > > > > the trouble is that PG0 isnt specific to the BF527 SDP board. if you > > read the HRM, PG0 is the default HWAIT signal for all BF52x procs. and > > iirc, you can change this in the OTP. i dont have a BF52x HRM handy atm > > to refresh my memory on the specifics. > > I don't know what HWAIT stands for. I cannot think it's related to > flash enable signal from the name. If you have named it as > sig_flash_enable and sig_flash_enable_level, I might have read the > related code carefully. I thought it was some kind of hack from the > first look. I think it will be better to make a patch to rename it to > something more meaningful.
HWAIT is the "hardware wait" signal. the Blackfin bootrom drives this to
signal so that the device it is loading from knows when to send data and when
to hold. think of it as CTS/RTS on a UART (after all, that's exactly how the
HWAIT signal gets used in UART boot mode).
when it comes to parallel flashes, the bootrom drives PG0 as its HWAIT signal.
the SDP board is tricky in that it is trying to minimize interference from its
own board so that it can expose as much of its lower pins as possible to the
USB side so that people can maximize the prototyping capabilities. since
parallel flash sucks up quite a lot of the async bank, it uses the PG0 as a
part of its trick: if PG0 is not being driven, then none of the async pins
route to the flash. instead, they route to the connector so people can use
them for something else. so when the processor is booting, the bootrom drives
PG0, and the flash is readable. when the processor is done, it stops driving
PG0, and the flash is no longer accessible.
> > i dont mind adding an alias for it, but it shouldnt be a dedicated board
> > like this.
> >
> >> Is there a way to put bf527_sdp into bf537_stamp.c like setting a
> >> default value to hwait and hwait_level?
> >
> > we might have to restructure a little to make it simpler ...
>
> After some thinking, I come up with this patch. The code can be
> extended for several more boards like bf527_sdp, but will not look
> pretty for more than that. What do you think?
hmm, how about we extend bfin_bus_new() to accept a default array structure ?
and that func can search the array for matching bus/key tuples ? that way we
can easily do this for all procs.
blackfin.h:
struct bfin_bus_defaults {
const char *bus_name;
int key;
const char *signal;
};
bf537_stamp.c:
static const bf537_stamp_defaults[] = {
{ "bf527_sdp", URJ_BUS_PARAM_KEY_HWAIT, "PG0", },
};
thinking about it a bit more, we could probably do this globally for all
buses, but for now let's implement it in the Blackfin bus core and see how it
goes. i know how much Chad loves you implementing my grand ideas out of scope
of your original needs ;).
-mike
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