Hello all, I have a few boards equipped with ONFI capable NAND flashes, and I would like to create flash support to the urjtag. Unfortunatelly I have no debugger to the core (PowerPC), so the boundary scan is the only way to access them.
The implementation way brings up a few question. Recently I have read the thread on the SPI flash support, so I would like to be clarfy myself about the implementation scheme before I start coding. The Open NAND Flash Interface specs are available free from here: http://onfi.org/ Currently the connection layer between the bus and flash drivers is based on reading/writing values to a specified address. The NAND bus behaves different: it is based on writing command or data. On the bus layer I would like to add three new functions to the URJ_BUS_DRIVER: int (*write_onfi_command) (urj_bus_t *bus, uint32_t command); int (*write_onfi_address) (urj_bus_t *bus, uint32_t address); uint32_t (*read_onfi_data)(urj_bus_t *bus); The other flash related commands (detectflash, flashmem, erase, lock) should be separated on the bus type, because they are heavily using the CFI related structures. Please review, comment the idea. Thanks, Miklós ------------------------------------------------------------------------------ Write once. Port to many. Get the SDK and tools to simplify cross-platform app development. Create new or port existing apps to sell to consumers worldwide. Explore the Intel AppUpSM program developer opportunity. appdeveloper.intel.com/join http://p.sf.net/sfu/intel-appdev _______________________________________________ UrJTAG-development mailing list [email protected] https://lists.sourceforge.net/lists/listinfo/urjtag-development
