Hi,
I am trying to get UrJTAG working with a XIlinx Kintex7 FFG676, but
have some troubles with the BSDL file.
>From Xilinx ISE 14.2 I have found the bsd file for the given chip in
/opt/Xilinx/14.2/ISE_DS/ISE/kintex7/data/xc7k325t_ffg676.bsd
This bsd uses STD_1149_6_2003, which I have been unable to find,
except in "The Boundary-Scan Handbook", at Google books [1].
I tried to copy the text into /usr/share/urjtag/bsdl/STD_1149_6_2003,
but I keep getting errors like:
ck@ck-move:~/gen_jtag$ bsdl2jtag xc7k325t_ffg676.bsd xc7k325t_ffg676
error: -E- error: In Package STD_1149_6_2003, Line 11, Error in
User-Defined Package declarations.
error: -E- error: BSDL file 'xc7k325t_ffg676.bsd' contains errors in
VHDL stage, stopping
error: vhdl subsystem: Parser error, see log for details
Something might be missing from the STD_1149_6_2003?
If I remove "use STD_1149_6_2003.all" from the BSD, I get five
different "Unsupported BSDL construct found". These are:
=> Number 1
attribute PORT_GROUPING of XC7K325T_FFG676 : entity is
"DIFFERENTIAL_VOLTAGE (" &
"(MGTXRXP0_115, MGTXRXN0_115), " &
"(MGTXRXP0_116, MGTXRXN0_116), " &
"(MGTXRXP1_115, MGTXRXN1_115), " &
"(MGTXRXP1_116, MGTXRXN1_116), " &
"(MGTXRXP2_115, MGTXRXN2_115), " &
"(MGTXRXP2_116, MGTXRXN2_116), " &
"(MGTXRXP3_115, MGTXRXN3_115), " &
"(MGTXRXP3_116, MGTXRXN3_116), " &
"(MGTXTXP0_115, MGTXTXN0_115), " &
"(MGTXTXP0_116, MGTXTXN0_116), " &
"(MGTXTXP1_115, MGTXTXN1_115), " &
"(MGTXTXP1_116, MGTXTXN1_116), " &
"(MGTXTXP2_115, MGTXTXN2_115), " &
"(MGTXTXP2_116, MGTXTXN2_116), " &
"(MGTXTXP3_115, MGTXTXN3_115), " &
"(MGTXTXP3_116, MGTXTXN3_116))";
=> Number 2
attribute AIO_COMPONENT_CONFORMANCE of XC7K325T_FFG676 : entity is
"STD_1149_6_2003";
=> Number 3
attribute AIO_EXTEST_Pulse_Execution of XC7K325T_FFG676 : entity is
"Wait_Duration TCK 15";
=> Number 4
attribute AIO_EXTEST_Train_Execution of XC7K325T_FFG676 : entity is
"train 30, maximum_time 120.0e-6";
=> Number 5
attribute AIO_Pin_Behavior of XC7K325T_FFG676 : entity is
"MGTXRXP0_115 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP0_116 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP1_115 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP1_116 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP2_115 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP2_116 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP3_115 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXRXP3_116 : LP_time=22.5e-9 HP_time=45.0e-9; " &
"MGTXTXP0_115; " &
"MGTXTXP0_116; " &
"MGTXTXP1_115; " &
"MGTXTXP1_116; " &
"MGTXTXP2_115; " &
"MGTXTXP2_116; " &
"MGTXTXP3_115; " &
"MGTXTXP3_116 ";
Number 2 to 5 is depending on the structure found in STD_1149_6_2003
and I guess this is why they don't work. As I read [1] the AIO
attributes are used for testing advance IOs and I assume that when I
only wants to program the device, I can skip this?
As I am using the Ubuntu version of UrJTAG (UrJTAG 0.10 #2007), error
number 1 might be similar to [2]
If I comment out the above code, bsdl2jtag will generate a file which
looks similar to the once shipping with UrJTAG for other device. But,
I am afraid that I might toast our FPGA :)
So, I basically have two questions:
1) Have everyone succeeded using UrJTAG with Xilinx Kintex7 or other
series 7 FPGAs?
2) Does my above assumptions seem ok? :)
Best regards
Christoffer Kjølbæk
[1]
http://books.google.dk/books?id=aUCgNOpyUbgC&lpg=PA308&ots=avOPFAXbo9&dq=use%20STD_1149_6_2003.all%3B%20bsdl&hl=da&pg=PA308#v=onepage&q=use%20STD_1149_6_2003.all;%20bsdl&f=false
[2] http://comments.gmane.org/gmane.comp.embedded.jtag.urjtag.devel/1283
--
Christoffer Kjølbæk
Electronics Designer, M.Sc.Eng
Move Innovation
Phone: +45 32 20 50 60
Email: [email protected]
Web: http://www.moveinnovation.dk
Generatorvej 8b st. | 2730 Herlev | Denmark
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