Hello, yes I have some ideas how to implement an interconnection test with UrJtag as JTAG bus master. I have also started implementing some of these ideas but for now I had to pause these actions as I moved into another town and also changed my place of work. I will continue my work on this project in a few weeks when my amount of free time is greater.
The basic ideas regarding this interconnection test are: - the test generator / executor will act as a client which connects to several UrJtag applications acting as servers - the connection between client / server will be a raw TCP socket - for the first tests I have used netcat at server side to provide the TCP connection - the client application manages several linked lists describing the UUT's structure (JTAG-chains which correspond to UrJtag-Servers, Devices in these chains, pins, nets) - I will provide functions to set attributes (like driven, high, low, open and weakly driven levels) for the nets and to define combinational logic functions between nets. The attributes are used to generate drive patterns and the logic functions are evaluated for the expect patterns. Later it will be possible to get these logical connections automatically via descriptions for non BScan devices. But at first I want to ignore these devices. It will also be possible to define sequential logic functions (like memorys) but this requires a more complex model. - The test pattern generation will be configurable to make it possible to have a fast test with worse diagnosis or a slower test with better diagnosis. Therefore I will use the concept of the counting sequence / modified / inverse counting sequence described by Parker in "The boundary scan handbook". Actually the test pattern generation is not this difficult. But the test generator should provide interfaces so the functionality may be increased later. One main principle will be to let the user know anything about the creation of the test patterns and the give him the possibility to control the generation. Thank you for your feedback. Please feel free to share your thoughts so this test generator can become a really useful tool. Kind regards Marco -----Ursprüngliche Nachricht----- Von: [email protected] [mailto:[email protected]] Gesendet: Mittwoch, 29. Juni 2016 14:07 An: [email protected] Betreff: UrJTAG-development Digest, Vol 81, Issue 1 Send UrJTAG-development mailing list submissions to [email protected] To subscribe or unsubscribe via the World Wide Web, visit https://lists.sourceforge.net/lists/listinfo/urjtag-development or, via email, send a message with subject or body 'help' to [email protected] You can reach the person managing the list at [email protected] When replying, please edit your Subject line so it is more specific than "Re: Contents of UrJTAG-development digest..." Today's Topics: 1. Re: automatically generated interconnection test (Markus Schneider) 2. Re: automatically generated interconnection test (Marco Behr) 3. Re: automatically generated interconnection test (Paul Fertser) 4. arduiggler cable with an ESP8266? (Benjamin Henrion) 5. Re: arduiggler cable with an ESP8266? (Kolja Waschk) 6. Patch for urjtag for USBprog 5 (Benedikt Sauter) ---------------------------------------------------------------------- Message: 1 Date: Tue, 5 Apr 2016 21:15:06 +0200 From: Markus Schneider <[email protected]> Subject: Re: [UrJTAG-dev] automatically generated interconnection test To: [email protected] Message-ID: <[email protected]> Content-Type: text/plain; charset=windows-1252 Hello, long time ago, I have made a urjtag extension for the Goepel Boundary Scan Coach, a Boundary Scan demo board. I have worked in the past also with Goepel tools and had the idea to create a pattern generator for a interconnection or memory test. But it was just a idea, and the lack of a powerful free available JTAG Bus master and the complexity of this task stops this attempt early. If you have ideas for pattern generator algorithms it would be interesting to revive the urjtag project. Markus Am 30.03.2016 um 12:18 schrieb Johann Klammer: > On 03/28/2016 08:00 PM, Marco Behr wrote: >> Hello, >> >> Are there any activities regarding an automatically generated >> interconnection test (for finding shorts/opens in a circuit) which uses UrJtag? >> >> I am using a commercial tool (Goepel electronics) for boundary scan >> tests in the company. Then I began looking for a non-commercial / >> open source tool which can do the same (with an low-cost hardware >> platform) so everyone at home can use it also. Soon I found UrJtag >> and OpenOCD as two possible platforms but neither one has a working implementation of this kind of test. >> >> In fact, UrJtag seems more convenient for adding such a function: >> - a working BSDL subsystem exists >> - a signal structure exists with commands for driving and testing >> digital values which can be extended by attributes defining the >> testability of these nets (Are other drivers connected to these nets? Are pull-resistors connected? >> ...) >> >> I would like to know if there is interest in adding such a function >> or if there are already some ideas on how this should look like? Are >> there any solutions on the internet which I haven't found looking for it? >> >> I have some experience with the commercial solutions and I am ready >> to spend some time in implementing a kind of interconnection test. >> Maybe I will be doing this as part of my master thesis, but the main >> goal should be to make this functionality available to the public. >> >> marco >> >> --------------------------------------------------------------------- >> --------- >> Transform Data into Opportunity. >> Accelerate data analysis in your applications with Intel Data >> Analytics Acceleration Library. >> Click to learn more. >> http://pubads.g.doubleclick.net/gampad/clk?id=278785471&iu=/4140 >> > I have used urjtags .svf replay capability to do test vector injection in a CPLD. > the .svf file was generated by a program. You may be able to modify it to your needs. > The code is not device-specific, so it'll work if you have a bsdl file. > > <https://github.com/klammerj/vec2svf> > > Things to look out for: > > urjtag does not handle multiple device chains correctly, so you'll > have to modify their .svf stuff if you want it to work(vec2svf can't handle it either). > > vec2svf acitvely(!) drives values onto the device I/Os then reads out > the device internal values for I/O and port-enables. This is likely > not what you want for your use-case(other stuff may be connected/destroyed). > You'll likely have to modify that. > > > > ---------------------------------------------------------------------- > -------- _______________________________________________ > UrJTAG-development mailing list > [email protected] > https://lists.sourceforge.net/lists/listinfo/urjtag-development > > ------------------------------ Message: 2 Date: Thu, 07 Apr 2016 20:28:15 +0200 From: Marco Behr <[email protected]> Subject: Re: [UrJTAG-dev] automatically generated interconnection test To: Paul Fertser <[email protected]>, [email protected] Message-ID: <6163108.O7rTbtUjQy@marco-gn598aa-abd-m8180-de> Content-Type: text/plain; charset="us-ascii" Hello Paul, thanks for your quick reply. I was not available a few days so I couldn't answer earlier. > Hello Marco, > > Speaking as an OpenOCD "fan" here, so please excuse my bias and > writing off-list :) > > On Mon, Mar 28, 2016 at 08:00:50PM +0200, Marco Behr wrote: > > I am using a commercial tool (Goepel electronics) for boundary scan > > tests in the company. Then I began looking for a non-commercial / > > open source tool which can do the same (with an low-cost hardware > > platform) so everyone at home can use it also. Soon I found UrJtag > > and OpenOCD as two possible platforms but neither one has a working > > implementation of this kind of test. > > Yes, UrJTAG has BSDL parser integrated but I'm not sure what real > advantage that gives. When one is testing something manually he can > easily interpret BSDL himself and I wrote some additional OpenOCD > scripts to be able to do boundary scan, see here[1]. The BSDL parser is good for quickly collecting ALL the information in the BSDL file. For an manually written test, it works fine when you only look for a single ports BScan cells and then write test pattern to them. But what I want to do is to define attributes for all reachable ports on the chip so the software can automatically generate big test vectors (e.g. using the counting pattern algorithm described by Kenneth P. Parker in his patent EP 0543506 B1) to detect shorts / opens between many nets. > But when it comes to automating it, my guess is that the most > straightforward way would be to write an SVF file generator. With > OpenOCD you can playback SVF with any kind of adapter, be it cheap > J-Link clone, FTDI-based device or even just about any Single Board > Computer (and for RaspberryPi there's a dedicated fast driver). Yes, SVF might be an option and both OpenOCD and UrJtag are able to play them. (And I think a few more software platforms can do this). But neither one can play SVF files on multiple devices. And furthermore tests on multiple JTAG chains simultaneously are absolutely not possible. So I think SVF might only solve a part of the problem. > There's also an OpenOCD enthusiast that has just shared a Python > parser for BSDL[2]. I think if you take something like that and > generate an SVF file from Python, playing it back with OpenOCD would > be a nice way to test your hardware. I had a look at this Python based parser - unfortunately I am completely new to Python. Although this one looks interesting and I will consider using it too. > Please feel free to share your thoughts and needs on the openocd-devel > mailing list. As I already said, I am thinking also about implementing these functions into OpenOCD instead of UrJtag. + there is much more activity at the OpenOCD project than at UrJtag the + Jim-Tcl implementation is also pretty useful - the main object of OOCD is debugging of software - not testing / debugging of circuits - OpenOCD doesn't allow multiple devices in a chain to be active (not bypassed) > Good luck, > And happy hacking :) > > [1] https://sourceforge.net/p/openocd/mailman/message/31069985/ > [2] https://github.com/cyrozap/python-bsdl-parser Thank you for your ideas - I will share this also on the OpenOCD mailing list ------------------------------ Message: 3 Date: Fri, 8 Apr 2016 16:04:27 +0300 From: Paul Fertser <[email protected]> Subject: Re: [UrJTAG-dev] automatically generated interconnection test To: Marco Behr <[email protected]> Cc: [email protected] Message-ID: <[email protected]> Content-Type: text/plain; charset=us-ascii Hey Marco, Quick reply as I'm away on vacation atm. On Thu, Apr 07, 2016 at 08:28:15PM +0200, Marco Behr wrote: > - OpenOCD doesn't allow multiple devices in a chain to be active (not > bypassed) To the best of my knowledge, when you play back an SVF with OpenOCD you have an opportunity to treat as many device as you need. You just do not specify the specific TAP in "svf" command and that's it, you have full control. Or am I missing something? -- Be free, use free (http://www.gnu.org/philosophy/free-sw.html) software! mailto:[email protected] ------------------------------ Message: 4 Date: Thu, 14 Apr 2016 10:32:25 +0200 From: Benjamin Henrion <[email protected]> Subject: [UrJTAG-dev] arduiggler cable with an ESP8266? To: UrJTAG developer mailing list <[email protected]> Message-ID: <canjd3ncyxv5solxkem_jzlc4gjnepjrntjrm-c9j6yqkym6...@mail.gmail.com> Content-Type: text/plain; charset=UTF-8 Hi, I have reposted some urjtag forked version which adds support for Arduiggler cable (cable made a of an FT232-based arduino): https://github.com/zoobab/urjtag-arduiggler/ The code compiles fine, but it only supports FTDI based arduinos, and I have had a recent request to add support for an Arduino Uno v3, which has an USB-serial adaptor based on an Atmel 16u2. I also want to add support for an ESP8266 based board, the Wemos D1 Mini, which has a ch340g usb converter. Is there any code to handle usb-serial converters other then ftdi ft232 ones? I presume it should have been done at some point by someone? Best, -- Benjamin Henrion <bhenrion at ffii.org> FFII Brussels - +32-484-566109 - +32-2-3500762 "In July 2005, after several failed attempts to legalise software patents in Europe, the patent establishment changed its strategy. Instead of explicitly seeking to sanction the patentability of software, they are now seeking to create a central European patent court, which would establish and enforce patentability rules in their favor, without any possibility of correction by competing courts or democratically elected legislators." ------------------------------ Message: 5 Date: Sun, 17 Apr 2016 13:04:10 +0200 From: Kolja Waschk <[email protected]> Subject: Re: [UrJTAG-dev] arduiggler cable with an ESP8266? To: [email protected] Message-ID: <[email protected]> Content-Type: text/plain; charset=windows-1252; format=flowed Hi, > Is there any code to handle usb-serial converters other then ftdi ft232 ones? One could talk to such adapters/cables over standard serial interface, or am I wrong? I.e. COM-port or /dev/ttyUSBx. It shouldn't be necessary to support each particular vendor-specific low level USB protocol, unless special features of a particular chip like bit banging are used. Regards, Kolja ------------------------------ Message: 6 Date: Wed, 29 Jun 2016 06:26:39 +0200 From: Benedikt Sauter <[email protected]> Subject: [UrJTAG-dev] Patch for urjtag for USBprog 5 To: [email protected] Message-ID: <[email protected]> Content-Type: text/plain; charset="utf-8" Hello, we create a patch for the usbprog 5. It is an embedded linux based programmer (www.usbprog.org <http://www.usbprog.org/>) https://github.com/embeddedprojects/usbprog5 <https://github.com/embeddedprojects/usbprog5> Inside there is an LPC3131 from NXP. We used direct the SPI interface to do jtag. If you a intrestested you can add our source to the project. Regards Benedikt Benedikt Sauter M.Sc., Dipl.-Inf. (FH), Gesch?ftsf?hrer Tel +49 821 27 95 99 0 Fax +49 821 27 95 99 20 [email protected] <mailto:[email protected]> www.embedded-projects.net <http://www.wawision.de/> ????????????????????????????????????????? embedded projects GmbH Holzbachstra?e 4 D-86152 Augsburg Sitz der Gesellschaft: Augsburg Handelsregister: Augsburg, HRB 23930 Gesch?ftsf?hrung: Dipl.-Inf.(FH) Benedikt Sauter M.Sc. UStIdNr.:DE263136143 -------------- next part -------------- An HTML attachment was scrubbed... -------------- next part -------------- A non-text attachment was scrubbed... Name: urjtag-0.10.patch Type: application/octet-stream Size: 204971 bytes Desc: not available -------------- next part -------------- An HTML attachment was scrubbed... ------------------------------ ---------------------------------------------------------------------------- -- Attend Shape: An AT&T Tech Expo July 15-16. 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