On Wed, Dec 11, 2019 at 05:54:41PM +0100, Jiri Gaisler wrote: > Hello, > > would there be any interest to include a debug monitor for LEON3/GRLIB > processors to urjtag? It allows to display various processor registers > and upload and execute programs. I have developed it similar to the > Blackfin module in urjtag, and it is of similar size. I have attached > the diff statistics and the README file. Let me know if there is any > interest to merge this into urjtag
My interest is having/getting many people who have interest in urjtag. So, yes, I'm willing to merge the grlib debugger. > or if I rather should have in a separate repo ... Your call ;-) > Jiri. > > From ee246a8359d4ab7e43afdf4774333f0a9ed969d2 Mon Sep 17 00:00:00 2001 > From: Jiri Gaisler <j...@gaisler.se> > Date: Mon, 9 Dec 2019 14:25:32 +0100 > Subject: [PATCH 0/1] *** SUBJECT HERE *** > > *** BLURB HERE *** > > Jiri Gaisler (1): > Added grlib subsystem > > urjtag/ChangeLog | 3 + > urjtag/MAINTAINERS | 7 + > urjtag/configure.ac | 1 + > urjtag/doc/README.grlib | 99 + > urjtag/include/urjtag/error.h | 2 + > urjtag/include/urjtag/grlib.h | 73 + > urjtag/src/Makefile.am | 2 + > urjtag/src/cmd/Makefile.am | 3 +- > urjtag/src/cmd/cmd_grlib.c | 270 +++ > urjtag/src/global/log-error.c | 2 + > urjtag/src/grlib/Makefile.am | 35 + > urjtag/src/grlib/devices.h | 291 +++ > urjtag/src/grlib/elf.c | 288 +++ > urjtag/src/grlib/elf.h | 3789 ++++++++++++++++++++++++++++++++ > urjtag/src/grlib/gdb.c | 570 +++++ > urjtag/src/grlib/grlib.c | 739 +++++++ > urjtag/src/grlib/grlib_int.h | 367 ++++ > urjtag/src/grlib/sparc.c | 138 ++ > urjtag/src/grlib/sparc.h | 155 ++ > urjtag/src/grlib/sparc_disas.c | 1083 +++++++++ > 20 files changed, 7916 insertions(+), 1 deletion(-) > create mode 100644 urjtag/doc/README.grlib > create mode 100644 urjtag/include/urjtag/grlib.h > create mode 100644 urjtag/src/cmd/cmd_grlib.c > create mode 100644 urjtag/src/grlib/Makefile.am > create mode 100644 urjtag/src/grlib/devices.h > create mode 100644 urjtag/src/grlib/elf.c > create mode 100644 urjtag/src/grlib/elf.h > create mode 100644 urjtag/src/grlib/gdb.c > create mode 100644 urjtag/src/grlib/grlib.c > create mode 100644 urjtag/src/grlib/grlib_int.h > create mode 100644 urjtag/src/grlib/sparc.c > create mode 100644 urjtag/src/grlib/sparc.h > create mode 100644 urjtag/src/grlib/sparc_disas.c > > -- > 2.17.1 > > > Overview > -------- > > The grlib subsystems allows scanning of IP cores in a grlib SOC system, > and executing of programs on a leon3 processor. Communication with the > hardware is done using the grlib AHBJTAG debug interface using any supported > JTAG cable. A suitable command file for the Pender Elextronics XC6SLX75 board > would be: > > cable FT2232 vid=0x0403 pid=0x6010 driver=ftdi-mpsse > detect > initbus ahbjtag > grlib scan > > The output of urjtag would then be: > > > Connected to libftdi driver. > IR length: 6 > Chain length: 1 > Device Id: 00000100000000001110000010010011 (0x0400E093) > Manufacturer: Xilinx (0x093) > Part(0): xc6slx75 (0x400E) > Stepping: 0 > Filename: /usr/local/share/urjtag/xilinx/xc6slx75/xc6slx75 > > Scanning GRLIB system, build version 4241 > > AHB Masters > LEON3 SPARC V8 Processor > LEON3 SPARC V8 Processor > LEON3 SPARC V8 Processor > AHB Debug UART > JTAG Debug Link > GR Ethernet MAC > > AHB Slaves Memory Range > LEON2 Memory Controller 0x00000000 - 0x20000000 > AHB/APB Bridge 0x80000000 - 0x80100000 > LEON3 Debug Support Unit 0x90000000 - 0xa0000000 > Xilinx MIG DDR2 Controller 0x40000000 - 0x48000000 > AHB/APB Bridge 0x80100000 - 0x80200000 > > APB Slaves > LEON2 Memory Controller 0x80000000 - 0x80000100 > Generic UART 0x80000100 - 0x80000200 > Multi-processor Interrupt Ctrl. 0x80000200 - 0x80000300 > Modular Timer Unit 0x80000300 - 0x80000400 > AHB Debug UART 0x80000700 - 0x80000800 > General Purpose I/O port 0x80000a00 - 0x80000b00 > General Purpose I/O port 0x80000b00 - 0x80000c00 > General Purpose I/O port 0x80000c00 - 0x80000d00 > AHB Status Register 0x80000d00 - 0x80000e00 > GR Ethernet MAC 0x80000e00 - 0x80000f00 > Xilinx MIG DDR2 Controller 0x80100000 - 0x80100100 > Gaisler RGMII Interface 0x80101000 - 0x80102000 > > Detected frequency from GPTIMER: 50.0 MHz > UART1 @ 0x80000100 enabled at 38400 baud > 128 MByte RAM @ 0x40000000, stack pointer 0x47ffffc0 > LEON3DSU @ 0x90000000, 3 processor(s) detected > jtag> > > The interaction with the SOC is done using the grlib command: > > grlib break Stop (break) running program > grlib cont Resume stopped program > grlib init Scan SOC and initialize IP cores > grlib load <file> Load ELF file to memory > grlib mem [addr] [bytes] Display memory > grlib run Run loaded ELF file > grlib rundb Run loaded ELF file, output to urjtag console > > A debug session could look like this: > > jtag> grlib load dhry.exe > SPARC executable > section: .text at 0x40000000, size 53296 bytes > section: .data at 0x4000d030, size 2764 bytes > Loaded 56060 bytes (387.6 kbit/s), entry 0x40000000, > jtag> grlib mem 0x40000000 > address 0x0 0x4 0x8 0xC ascii > 0x40000000 88100000 0910002D 81C12344 01000000 .......-..#D.... > 0x40000010 A1480000 A7500000 10802DC5 AC102001 .H...P....-... . > 0x40000020 91D02000 01000000 01000000 01000000 .. ............. > 0x40000030 91D02000 01000000 01000000 01000000 .. ............. > jtag>grlib run > <output on board console (e.g. /dev/ttyS0> > > > Limitations > ----------- > > * Only IP cores from the GPL version of grlib are detected and supported > * leon3 MMU not supported > * Only memory controller currently supported is MIGDDR2 > * No breakpoint/watchpoint support (yet) > Cool! Groeten Geert Stappers -- Leven en laten leven _______________________________________________ UrJTAG-development mailing list UrJTAG-development@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/urjtag-development
