I work for a small EDA company that simulates Verilog designs. One feature of Verilog is a rich capability for expressing constraints on sets of variables. We can currently handle simple constraint sets but believe it will be beyond our resources to develop in house, a sophisticated constraint solver. Gecode caught my eye as a possibility. Our code base is C/C++. I was wondering if anyone here has successfully used Gecode to solve Verilog constraints?
Thanks, Bob P
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