Hello Stefan,
On 09/03/2021 20:11, Stefan Akatyschew wrote:
core 1 is stuck at an IRQ intialisation routine (in irq/irq-gic.c) for
ditto?
I can't really debug the second core somehow. Though Trace32 is supposed
to step through core 0 and 1 simultaniously (in SMP), it does only work
on core 0 for me. Trying to do that on core 1 results in bus error for me...
All I see is it being stuck at : irq/irq-gic.c:157
BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void)
I would try to fix the debug issues on core 1 so that you can debug the
startup reliably. You can also contact the Lauterbach support.
From the screenshots you see that core 0 waits for the core 1 to
perform some parts of the clock driver initialization. However, core 1
waits in a very early step for an initialized interrupt controller
(which was already done by core 0). Is the address of the GIC
Distributor all right on core 1? If you look at the register via the
Lauterbach peripheral view, is the Distributor enabled?
Maybe there is an issue with the MMU setup on core 1. You can check the MMU
initialization with the Lauterbach. The GIC area has to be a Device memory.
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