This is Gaurav, working with SysMind. We have the below contract job opportunity with one of our direct clients and would like to check if you have any resources available. Please send across the resume of your consultants along with the contact information at the earliest to [email protected] or call me at 609-897-9670 X2154
Role: VLSI Engineer (ASIC Design) Location: Santa Clara ,CA Duration: 6+ Months Interview type: Telephonic/Skype Description: *Skill1 - Hardware Designing* Responsible for the schematic entry, circuit design, circuit debugging, simulation, layout & verification of complex components of a chip block. Works on problems of relatively complex scope, through general usage of standard design concepts and principles and application of own judgment. Works as a fully contributing team member, under broad supervision/ guidance. Requires solid knowledge of at least one design area. Expected to further build upon domain knowledge and technical/ proprietary skills to reach levels of expertise. May guide new members in the team to help them scale up faster *Skill2 - Technical Consulting* Contributes to a project by analyzing technology used by the client and designing the solution. Preparation of Business Blueprint, System configuration and set up, Test scenarios, End-User documentation , user manuals and other implementation tasks and gain acceptance from the customer. Participate in implementation of business solutions. Has moderate to heavy contact with middle and senior level executives at the client. Requires proven project management skills. May have an expertise or comprehensive knowledge of a particular technical specialty. Has a good understanding of multiple domain areas with linkage to various technologies. *Essential Skill-* *Skill1 - ASIC Design* Competent in basic digital design concepts, boolean arithmetic, decoding, interfacing, clocking, setup-hold timing concepts, Able to perform low level design involving control and data path designs Multi-clock design skills., Good documentation skills., can create a module level design document involving protocols amd can efficiently transform that to an HDL description. Able to perform high level design can create a full IP level design document; is capable of reviewing design documents created by others; is capable of making power/area/speed trade-offs. Is capable of developing debug strategy for the design. Is capable of IP selection, bus fabric implementation, full chip integration, is aware of verification/DFT/PD friendly full chip implementation. Gaurav Nagar Phone: 609-897-9670 x2154 Email: [email protected] Fax: 609-228-5522 Address: 38 Washington Road, Princeton Jn, NJ 08550 -- You received this message because you are subscribed to the Google Groups "USITCV" group. To unsubscribe from this group and stop receiving emails from it, send an email to [email protected]. To post to this group, send email to [email protected]. Visit this group at http://groups.google.com/group/usitcv. For more options, visit https://groups.google.com/groups/opt_out.
