Dear Folks,

We Have Excellent Mainframe Consultant/ASIC Design Engineer for your
Direct Client Requirements.
Please forward me Requirements if you have on your desk directly to me
at
[EMAIL PROTECTED]

Mainframe Consultant : Lizziga Jeyasingh
Status                              : H1B
Available                        : Immediately
Location                          : San Antonio,TX
LIZZIGA JEYASINGH
��      Over 7.5 years of experience in Mainframe Application Development,
Maintenance, Production Support, Analysis, Design, Testing &
Implementation.
��      Enhancements and evaluation of Banking system, Insurance/Investment,
Manufacturing, Telecom/Billing and Financial Applications.
��      Experience in execution of projects through all phases of SDLC
(Software Development Life Cycle) which includes Requirement gathering
& Analysis, Data Analysis, Design, Coding, Reviews, Documentation,
Different Quality and Process methodologies, Unit testing, System/
Integration Testing, UAT Support, Volume Testing, Production
Implementation, and production support.
��      Extensive experience in COBOL, JCL, VSAM, SQL, DB2, IMS DB/DC, CICS,
FOCUS, SAS, Visionplus, and IBM tools & utilities.
��      Solid knowledge & experience working with most of the Mainframe
application tools & Utilities like FileAid, File Manager, Insync,
SYNCSORT, DFSORT, ICETOOL, Easytrieve, REXX, ChangeMan, Endevor,
ESP(Execution Schedule Processor), OPC, Expeditor, Trace Master,
Smartest, Intertest, Abend-Aid, TSO/ISPF, SPUFI, QMF, NDM, FTP, SAR-
View, CA-7.

TECHNICAL SKILLS

Operating Systems               :  MVS-ESA, OS/390, Z/OS, Windows NT/XP/2000,
                    UNIX, DOS, Novell Netware
Languages                       :  COBOL II/III, VMS COBOL, SAS, FOCUS, SQL
Middle Ware                     :  JCL, VSAM, SQL, MQ Series
Database                        :  IBM DB2, IMS-DB
Online Processing               :  CICS, IMS-DC
Business Intelligence Tools     :  Business Objects XI R2/6.5
Data Transfer                   :  Connect Direct(C: D), NDM, FTP
File Processing Tools           :  File Aid-MVS/IMS, File Manager, Insync
Debugging Tools                 :  Expeditor, IBM Debugging tool, Smartest,
Intertest,
                                                Trace Master, Abend-
Aid Fault Analyzer
Version Controller              :  ChangeMan, Endevor, Pan Valet
Job Scheduler                   :  CA-7/CA-11, ESP (Execution Schedule 
Processor),
                                                ZEKE Scheduler, OPC
Reporting                       :  SAR Reports, Control-D, Easytrieve, FOCUS/SAS
                                                Reports, MOBIUS
Other Tools                     :  TSO/ISPF, QMF, SPUFI, SYNCSORT, DFSORT,
                                                ICETOOL, Remedy/
Clarify, RC/Update, SAR-View
Microsoft Products              :  Microsoft Office Suite, MS VISIO
Process Tools                   :  Test Director, STAR Team, Mercury Quality 
Center,
                                                Visual SourceSafe,
QTP, Work Bench (WBS), Clarity,
                                                PM Sheets
Mailing Systems         :  Lotus Notes, MS Outlook Express

RAJARATHINAM


VLSI ASIC/FPGA Design / Verification Engineer


NAME                                    Rajarathinam Raghupathi

QUALIFICATION                   Bachelor of Engineering in Electronics and
 
Communication Engineering

HARDWARE                                Sun Workstations and PC

OPERATING SYSTEM                Windows ‘9X, 2003, Windows NT, Linux

LANGUAGES                       VHDL, Verilog, e (intermediate)

SCRIPT                                              Shell and Perl

TOOLS                               ModelSim, Visual HDL, Active HDL, Cadance
                                                            NCVHDL,
Simvision, Leonardo Spectrum [Level 3],
                                                            Xilinx
ISE, FPGA Advantage, Verdi, Accurev.


SUMMARY OF PROFESSIONAL EXPERIENCE

Rajarathinam R has 7 years of experience. His area of expertise is
design, synthesis, PAR and verification of ASIC/FPGA. He is Proficient
in VHDL, Verilog, Perl and LINUX.  He has worked on tools like
XilinxISE, Modelsim, Leonardo Spectrum (Level-3), Active VHDL, Cadance
NCVHDL and Visual HDL. Knowledge in ‘e’ language and Specman Elite.
Also, he has very good technical capabilities.


Thank you Very much,
Naren,
Recruiter
Tiny Planet Inc.
[EMAIL PROTECTED]
562*275*3541
www.tinyplanetinc.com




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