VERIFICATION ENGINEER
RATE: DOE LOCATION: SILICON VALLEY, CA DURATION: 12 MONTHS 1. Verification Engineer with good experience in SV with PCIE, AHB, SATA, etc.(Silicon Valley) 2. Senior Design Engineer with good experience with video domain, Verilog, VHDL (Silicon Valley) 3. Senior Design Engineer with good experience with ARM9, AHB, PCIE, SATA, etc. (Silicon Valley) 4. Verification Engineer with very good experience with VERA & SV (VERA is MUST) (Silicon Valley) 5. Verification Engineer with good experience with PCIE & VERA (Portland) If you have any queries, please feel free to call me or email me back. Thanks and have a great day !!!! Shelly Sr. Resource Manager Silicon Valley Systech Inc. Tel: 408-335-0405 Ext-202 | Fax: 408-727-5601 [EMAIL PROTECTED] <http://www.svsservices.com> www.svsservices.com --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "USITSOFT" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.com/group/usitsoft?hl=en -~----------~----~----~----~------~----~------~--~---
