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Today's Topics:
1. Re: Problem with DBSRX2 USRP1 Simulink (Mike McLernon)
2. Re: timing constraints and resource utilization for usrp2
fpga code (Arun Pillai)
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Message: 1
Date: Wed, 23 Mar 2011 11:46:34 +0000
From: Mike McLernon <[email protected]>
To: Paola Madonna <[email protected]>
Cc: "[email protected]" <[email protected]>
Subject: Re: [USRP-users] Problem with DBSRX2 USRP1 Simulink
Message-ID:
<e3879be9a282cb45aab7ce258a9ae48f05b53...@exmb-01-ah.ad.mathworks.com>
Content-Type: text/plain; charset="us-ascii"
Hello Paola,
The current USRP2 (not USRP1) Simulink I/O blocks work with a UDP driver, not a
UHD driver. MathWorks will be releasing UHD-based I/O blocks in the near
future.
Is there a reason you bought the USRP1 instead of a USRP2 or an N210?
Hth,
Mike
From: [email protected]
[mailto:[email protected]] On Behalf Of Paola Madonna
Sent: Wednesday, March 23, 2011 6:11 AM
To: [email protected]
Subject: [USRP-users] Problem with DBSRX2 USRP1 Simulink
Hello,
I have bought a USRP1 and a DBSRX2 dautherboard. I have installed the drivers
for Simulink as indicated in your web site but the dautherboard results unknown
using the block user_helper in the USRP library of Simulink and so it doesn't
acquire the gps signal from antenna. I have read on your website that the
DBSRX2 needs UHD driver so the driver installed recognizes only the motherboard
USRP1 and not the dautherboard. Now I am installing UHD driver under windows
but I am asking how to use the uhd driver with Simulink and if I can use the
USRP library of Simulink as indicated on your website.
Please help me as soon as possible.
Greetings,
--------------------------------
Ing. Paola Madonna
TRS S.p.A.
Via Giulio Cesare 105
c/o Selex-SI, Stab. Fusaro
80070 Bacoli (NA)
Italy
Ph.:+39 (0)81 52 72 837
Fax: +39 (0)81 52 72 828
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Message: 2
Date: Wed, 23 Mar 2011 09:02:25 -0400
From: Arun Pillai <[email protected]>
To: Nick Foster <[email protected]>
Cc: [email protected]
Subject: Re: [USRP-users] timing constraints and resource utilization
for usrp2 fpga code
Message-ID: <[email protected]>
Content-Type: text/plain; charset="utf-8"; Format="flowed"
I'm also attaching the twr to this mail.
On 03/23/2011 01:54 AM, Nick Foster wrote:
> On Wed, 2011-03-23 at 01:44 -0400, Arun Pillai wrote:
>> Hi,
>>
>> I downloaded and compiled the UHD fpga code for USRP2 using Xilinx 12.4.
>> However, its resource utilization seems way higher than the original
>> non-UHD fpga code that worked with Xilinx 10.3.
>
> The UHD image is doing a whole lot more than the non-UHD image did. You
> get UDP, real flow control, transmit buffering using the SRAM,
> synchronization, MIMO cable support, etc.
>
> <snip>
>
>> Also, the UHD code is failing to meet timing. Is this going to lead to
>> flakiness or problems when running the code? Are there options I can set
>> to get the code to meet timing, at the cost of greater compile time?
>
> Is it close, or is it totally missing timing? ISE's somewhat
> nondeterministic behavior means that different versions of ISE can
> produce very different results. We use 12.1, and the build meets timing.
>
> --n
>
>>
>> Thanks,
>> Arun
>>
>> _______________________________________________
>> USRP-users mailing list
>> [email protected]
>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
>
>
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