hello I use e310 and try to build custom fpga image. and i entered a trial license, including webPack, from Vivado License manager. In the View License Status tab, the license named Synthesis and XC7Z020 is displayed. However, i received error message saying that the license is not available. this is error log about command 'sudo ./uhd_image_builder.py window fft -d e310 -t E310_RFNOC_sg3 -m 5 --fill-with-fifos'. please tell me what is wrong.
thanks. spade@spade-DREAMPRO:~/rfnoc/src/uhd-fpga/usrp3/tools/scripts$ sudo ./uhd_image_builder.py window fft -d e310 -t E310_RFNOC_sg3 -m 5 --fill-with-fifos [sudo] password for spade: --Using the following blocks to generate image: * window * fft Adding CE instantiation file for 'E310_RFNOC_sg3' changing temporarily working directory to /home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/../../top/e300 Setting up a 64-bit FPGA build environment for the USRP-E3x0... - Vivado: Found (/opt/Xilinx/Vivado/2015.4/bin) - Vivado HLS: Found (/opt/Xilinx/Vivado_HLS/2015.4/bin) Environment successfully initialized. make -f Makefile.e300.inc bin NAME=E310_RFNOC_sg3 ARCH=zynq PART_ID=xc7z020/clg484/-3 RFNOC=1 E310=1 EXTRA_DEFS="RFNOC=1 E310=1" make[1]: Entering directory '/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300' BUILDER: Checking tools... * GNU bash, version 4.3.48(1)-release (x86_64-pc-linux-gnu) * Python 2.7.12 * Vivado v2015.4 (64-bit) ======================================================== BUILDER: Building IP axi_fft ======================================================== BUILDER: Staging IP in build directory... BUILDER: Reserving IP location: /home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft BUILDER: Retargeting IP to part zynq/xc7z020/clg484/-3... BUILDER: Building IP... ****** Vivado v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/spade/rfnoc/src/uhd-fpga/usrp3/tools/scripts/viv_generate_ip.tcl # set xci_file $::env(XCI_FILE) ; # set part_name $::env(PART_NAME) ; # set gen_example_proj $::env(GEN_EXAMPLE) ; # set synth_ip $::env(SYNTH_IP) ; # set ip_name [file rootname [file tail $xci_file]] ; # file delete -force "$xci_file.out" # create_project -part $part_name -in_memory -ip # set_property target_simulator XSim [current_project] # add_files -norecurse -force $xci_file INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'. # reset_target all [get_files $xci_file] # puts "BUILDER: Generating IP Target..." BUILDER: Generating IP Target... # generate_target all [get_files $xci_file] INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'axi_fft'... INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'axi_fft'... INFO: [Device 21-403] Loading part xc7z020clg484-3 INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'axi_fft'... INFO: [IP_Flow 19-1686] Generating 'C Simulation' target for IP 'axi_fft'... INFO: [IP_Flow 19-1686] Generating 'Test Bench' target for IP 'axi_fft'... INFO: [IP_Flow 19-1686] Generating 'Change Log' target for IP 'axi_fft'... generate_target: Time (s): cpu = 00:00:06 ; elapsed = 00:00:08 . Memory (MB): peak = 1134.184 ; gain = 162.906 ; free physical = 1258 ; free virtual = 6661 # if [string match $synth_ip "1"] { # puts "BUILDER: Synthesizing IP Target..." # synth_ip [get_ips $ip_name] # } BUILDER: Synthesizing IP Target... INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2015.4/data/ip'. Command: synth_design -top axi_fft -part xc7z020clg484-3 -mode out_of_context Starting synth_design Attempting to get a license for feature 'Synthesis' and/or device 'xc7z020' WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7z020' 1 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered. synth_design failed ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z020'. Please run the Vivado License Manager for assistance in determining which features and devices are licensed for your system. Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Common 17-53] User Exception: No open design. Please open an elaborated, synthesized or implemented design before executing this command. ERROR: [Vivado 12-398] No designs are open ****** Webtalk v2015.4 (64-bit) **** SW Build 1412921 on Wed Nov 18 09:44:32 MST 2015 **** IP Build 1412160 on Tue Nov 17 13:47:24 MST 2015 ** Copyright 1986-2015 Xilinx, Inc. All Rights Reserved. source /home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/.Xil/Vivado-2801-spade-DREAMPRO/webtalk/labtool_webtalk.tcl -notrace INFO: [Common 17-206] Exiting Webtalk at Wed Jul 26 09:38:41 2017... INFO: [Vivado 12-3441] generate_netlist_ip - operation complete # if [string match $gen_example_proj "1"] { # puts "BUILDER: Generating Example Design..." # open_example_project -force -dir . [get_ips $ip_name] # } # close_project # if { [get_msg_config -count -severity ERROR] == 0 } { # # Write output cookie file # set outfile [open "$xci_file.out" w] # puts $outfile "This file was auto-generated by viv_generate_ip.tcl and signifies that IP generation is done." # close $outfile # } else { # exit 1 # } INFO: [Common 17-206] Exiting Vivado at Wed Jul 26 09:38:42 2017... BUILDER: Releasing IP location: /home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft /home/spade/rfnoc/src/uhd-fpga/usrp3/lib/ip/axi_fft/Makefile.inc:15: recipe for target '/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft/axi_fft.xci' failed make[1]: *** [/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300/build-ip/xc7z020clg484-3/axi_fft/axi_fft.xci] Error 1 make[1]: Leaving directory '/home/spade/rfnoc/src/uhd-fpga/usrp3/top/e300' Makefile:56: recipe for target 'E310_RFNOC_sg3' failed make: *** [E310_RFNOC_sg3] Error 2
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