With help from Jonathon, this issue has been resolved. The basic steps taken that might assist others:
1) Used 4 RFNoC radio blocks for dual full duplex, used the dma fifo for the tx chains and reduced its size to limit the delay out to the antenna for low sample rates. 2) Implemented part of the tx chains in rfnoc (bpsk modulator + interpolating fir transmit filter) - this eliminated U's but caused packet drops indicated by Doverrun. 3) Running netstat -s before and after running the flowgraph and getting packet drops, check to see if the value of UDP: RcvBufErrors increases. If it does, drops are occurring in the kernel (so maybe host processing speed is an issue) otherwise they are likely occurring in the NIC. Check the NIC's ring buffer descriptor count 'ethtool -g eth0' mine was set for 256 for rx, change this to the max by running 'ethtool -G eth0 rx 4096' (probably good to do on the tx too). Flowgraph now runs without any errors! On Wed, Jul 26, 2017 at 12:54 PM, Michael Carosino <m.caros...@gmail.com> wrote: > Jonathon, > > I'm using 1GigE and running at 2Msps (and lower). Unfortunately I cannot > use jumbo frames (9000 mtu) as currently our x310's are on a network not > setup for them (which breaks other things if enabled). The weird thing is > the underruns only occur with the 4 rfnoc radio blocks, they don't occur if > I use a usrp source + sink each with 2 channels. I imagine there must be > some difference in how the data is passed in these two scenarios? Ideally I > would be able to change the dma fifo size directly in the usrp sink block, > however as a workaround, I'm trying to build my own fpga image with a > different default size for the dram tx fifo and hopefully then I can use > the usrp source/sink blocks again. > > The underruns don't happen with only 1 TX radio (assuming you use a usrp > sink or a rfnoc radio + dma fifo). > > thanks, > Michael > > On Jul 26, 2017 12:24 PM, "Jonathon Pendlum" <jonathon.pend...@ettus.com> > wrote: > > Hi Mike, > > Make sure your MTU is set to 9000. Are you using 1GigE or 10GigE? Do you > see underruns improve when running with only 1 TX radio? > > Jonathon > > On Tue, Jul 25, 2017 at 2:18 PM, Michael Carosino via USRP-users < > usrp-users@lists.ettus.com> wrote: > >> Hi, >> >> I'm using gnuradio 3.7.12 and rfnoc-devel commit 1908672. >> >> I'm trying to use both daughter boards on the x310 each at full duplex >> (that is, I will have 2 independent tx paths and 2 independent rx paths). >> So far I have accomplished this by using the UHD: USRP Sink/Source blocks >> and setting them to 2 channels, selecting the appropriate antennas, and >> specifying a subdev spec of A:0 B:0. The flowgraph works perfectly sending >> and receiving 2 sets of data simultaneously. >> >> However, I need to have the same capability when using the RFNoC blocks. >> I've attempted to use 2 RFNoC radio blocks, one set to Tx, 2 channels, and >> the other set to Rx, 2 channels, however the block's parameters have only a >> radio select of A or B unlike the usrp source's subdev spec, so this setup >> does not appear to work no matter what configurations I try. Am I mistaken >> about what the 2 channels refers to here? >> >> I did finally get an RFNoC setup that works by using 4 RFNoC radio blocks >> (2 for transmit with radio select A, B respectively, and 2 for receive with >> radio select A, B respectively). However, with this setup I get tons of >> underflow "U" in the console. Curiously this happens even when using the >> DMAFIFO as ettus recommends so I'm not sure what's going on. My flowgraph >> is attached showing this setup. >> >> (A quick note on why I want to use the rfnoc blocks, apparently the uhd >> usrp sink block now automatically includes a DMAFIFO in the tx chain to >> deal with the underflow issue caused by tcp flow control, however for my >> application the depth/size of this fifo is much too large and causing >> massive delays, I've found that by reducing the depth I can minimize my >> delay and I'll only get underflows on flowgraph startup which I assume is >> due to the tcp slow start phase before backoff occurs. All this to say, if >> there is a way to adjust the dma fifo depth from the usrp sink blocks I'd >> gladly use that instead). >> >> >> Thanks, >> Mike >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> > >
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