I've done it many times. When you open it and you do a save-as of the
project, make sure that you don't check the option box to copy the files
over, you want to leave them in their current location.
On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote:
Hi folks,
Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design
into Vivado 2015.4 and created the FPGA image using its graphical
Interface? I am still unable to do so.
I want to create a standard FPGA image using Vivado GUI.
I have first run the command /“//make X310_RFNOC_HG GUI=1”/, saved the
whole RTS design and reopened it as project mode, and then tried to
create the bitstream from the GUI itself but it doesn’t work.
I have also tried adding the x300.v file, the constraints and all its
dependent files into the design, and then done the synthesis,
implementation and generated the bitstream, but when I loaded it onto
the USRP I can’t recognize any block using the command uhd_usrp_probe.
This is the error I get:
[ERROR] [UHD] Exception caught in safe-call.
in virtual ctrl_iface_impl::~ctrl_iface_impl()
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76
this->peek32(0); -> EnvironmentError: IOError: Block ctrl
(CE_04_Port_70) no response packet - AssertionError: bool(buff)
in uint64_t ctrl_iface_impl::wait_for_ack(bool)
at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197
Best,
Luis A. Torres
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