Hi Jason/folks, Do you know how to generate an FPGA image from Vivado GUI that includes an OOT block created using rfnocmodtool?
I created an OOT block using rfnocmodtool, run a testbench to verify that it was ok, then generated a bit file with the uhd_image_builder.py script and programmed it onto the USRP successfully: I could see the custom block listed among the RFNoC blocks. However, when trying to create the same image from Vivado modifying the rfnoc_ce_auto_inst_x300.v file by including my own block and adding the dependent Verilog files to the design, even though I can run the synthesis/implementation and generate a bit file, after loading it to the URSP I can’t see any block. Do you know whether I have to modify some extra files apart from the rfnoc_ce_auto_inst_x300.v? The purpose behind this is to build images of new OTT blocks using exclusively Vivado GUI. Best, Luis Von: Jason Matusiak <ja...@gardettoengineering.com> Datum: Freitag, 18. August 2017 um 18:42 An: "Torres Figueroa, Luis Angel" <luis.torres.figue...@rwth-aachen.de>, "usrp-users@lists.ettus.com" <usrp-users@lists.ettus.com> Betreff: Re: [USRP-users] Building FPGA image I'm glad you got it working. There are a lot of critical warnings and things of that ilk that scroll by, but as long as you don't get any errors and your project meets timing, I wouldn't worry too much about them. Happy FPGAing. On 08/18/2017 09:26 AM, Torres Figueroa, Luis Angel wrote: Hi Jason, It worked. I downloaded the source files from rfnoc-devel branch in the repository again and build it without choosing the option you mentioned. I have still some critical warnings, but the image has been correctly generated and I could use it in the URSP. Also, all the timing constraints were now met. Thanks for the advice! ImplementationDesign Initialization [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'axi_hb31'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/axi_hb31/fir_compiler_v7_2_5/constraints/fir_compiler_v7_2.xdc will not be read for any cell of this module. [Designutils 20-1280] Could not find module 'fifo_4k_2clk'. The XDC file /home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/build-ip/xc7k410tffg900-2/fifo_4k_2clk/fifo_4k_2clk/fifo_4k_2clk_clocks.xdc will not be read for any cell of this module. [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":293] [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":294] [Common 17-55] 'set_property' expects at least one object. ["/home/rfnoc-devel/source/uhd/fpga-src/usrp3/top/x300/timing.xdc":295] Best, Luis Von: Jason Matusiak <ja...@gardettoengineering.com><mailto:ja...@gardettoengineering.com> Datum: Mittwoch, 16. August 2017 um 17:09 An: "Torres Figueroa, Luis Angel" <luis.torres.figue...@rwth-aachen.de><mailto:luis.torres.figue...@rwth-aachen.de>, "usrp-users@lists.ettus.com"<mailto:usrp-users@lists.ettus.com> <usrp-users@lists.ettus.com><mailto:usrp-users@lists.ettus.com> Betreff: Re: [USRP-users] Building FPGA image I've done it many times. When you open it and you do a save-as of the project, make sure that you don't check the option box to copy the files over, you want to leave them in their current location. On 08/16/2017 10:15 AM, Torres Figueroa, Luis Angel via USRP-users wrote: Hi folks, Has someone of you loaded the whole usrp_x310_fpga_RFNOC_HG design into Vivado 2015.4 and created the FPGA image using its graphical Interface? I am still unable to do so. I want to create a standard FPGA image using Vivado GUI. I have first run the command “make X310_RFNOC_HG GUI=1”, saved the whole RTS design and reopened it as project mode, and then tried to create the bitstream from the GUI itself but it doesn’t work. I have also tried adding the x300.v file, the constraints and all its dependent files into the design, and then done the synthesis, implementation and generated the bitstream, but when I loaded it onto the USRP I can’t recognize any block using the command uhd_usrp_probe. This is the error I get: [ERROR] [UHD] Exception caught in safe-call. in virtual ctrl_iface_impl::~ctrl_iface_impl() at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:76 this->peek32(0); -> EnvironmentError: IOError: Block ctrl (CE_04_Port_70) no response packet - AssertionError: bool(buff) in uint64_t ctrl_iface_impl::wait_for_ack(bool) at ~/uhd/host/lib/rfnoc/ctrl_iface.cpp:197 Best, Luis A. Torres _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com<mailto:USRP-users@lists.ettus.com> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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