Hi Adam, Can you post your testbench makefile?
Jonathon On Jan 10, 2018 5:07 PM, "Adam Parower via USRP-users" < usrp-users@lists.ettus.com> wrote: > Hello everyone, > > > I am trying to create a custom RFNoC block that is similar to the built-in > DUC block. As such, it depends on the cordic_timed, axi_rate_change, and > duc modules defined in uhd-fpga/usrp3/lib/rfnoc. When I attempt to run the > testbench for my block, Vivado fails in synthesis. While Vivado is able to > find cordic_timed.v, axi_rate_change.v, and duc.v, it is unable to find > the submodules that these modules depend on (e.g. axi_rate_change requires > setting_reg, axi_fifo_flop2, and axi_drop_partial_packet). What can I do to > get Vivado to find these dependencies and synthesize my block? > > > Thank you in advance for your assistance. > > > Adam Parower > > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > >
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