Dear all,
I have an USRP x310 device and I would like to modify the existing FPGA usrp3 design by adding Xilinx’s Viterbi decoder IP core to it. I was wondering if there’s any documentation regarding the FPGA design (block scheme) other that the one on the http://files.ettus.com/manual/md_fpga.html link? Thank you and regards, Ana Svircic --- Ova e-pošta je provjerena na viruse Avast protuvirusnim programom. https://www.avast.com/antivirus
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