Hi Jason, this just means that the loader can't even open the file you specified. It looks like you're missing the leading "/" of the absolute path you're specifying.
Best regards, Marcus On Fri, 2018-02-23 at 13:46 -0500, Jason Meyer via USRP-users wrote: > Hi, > > I am trying to build a custom FPGA image for my E312 device using > Ettus-provided RFNoC blocks with the UHD Image Builder GUI. I am able > to generate the bitstream, and attempted to load it onto the E312 > using the command: > > uhd_usrp_probe -- > args=”fpga=home/root/localinstall/usr/share/uhd/images/e310_test.bit” > > Where "e310_test.bit" is the generated bitstream. I got the following > error: > > Error: AssertionError: fpga_file.good() > in void uhd::usrp::e300::common::load_fpga_image(const > string&) > > This seems to be an error with the generated bitstream, is that > correct? And is there something I can do in the bitstream generation > process to prevent errors like this in the future? > > Thanks, > Jason > > _______________________________________________ > USRP-users mailing list > [email protected] > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list [email protected] http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
