Hi all,
When we set "master_clock_rate=25.6M" for Receiving and we found
that there is a Single frequency interference in
76.8M(25.6X3),102.4M(25.6X4),153.6M and so on until above 1.5G.We changed
the "master_clock_rate=16M",and we also found that there is a Single
frequency interference in 80M(16X5),96M(16X6)and so on.The signal power is
larger than noise about 5db.Is it the problem of the chip or the problem
of USRP E310?
thank you
best regards
Jon
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