Now I am able to get predictable (although not zero) phase offset with 122.88 MHz master clock. For that I have to use 12.288MHz reference frequency so zero delay mode of lmk04816 is applied.
thanks, Dmitry вт, 19 июн. 2018 г. в 19:38, Ian Buckley <i...@ionconcepts.com>: > Driven from pins 14 and 15 (10MEG_R_P/N) of SY89547 from page 12….that > page of FPGA pinning is redacted because it contains other proprietary info > that NI doesn’t want to release. > -Ian > > > On Jun 19, 2018, at 8:20 AM, Дмитрий Михайличенко via USRP-users < > usrp-users@lists.ettus.com> wrote: > > Just to clarify source of FPGA_REFCLK_10MHz_p/n signals (pins AG24, AH24). > I have not found them in the schematic. Do they come from SY89547 or from > LMK04816? > > thanks, > Dmitry > > пн, 18 июн. 2018 г. в 22:27, Ian Buckley via USRP-users < > usrp-users@lists.ettus.com>: > >> Dmitry , >> Yes that will cause you some pain. In this specific case the internal >> details of the X310 are important. >> The PPS is first sampled by a synchronizer (chain of registers) clocked >> with the REF_CLK. But then there is a secondary synchronizer to the DSP >> clock, which in the case of your modified UHD, is asynchronous w.r.t the >> 10MHz REF_CLK, so there is again a hazard of a violation of setup/hold >> timing on that secondary synchronizer as the relative phases shift with >> respect to each other, and hence a potential ambiguity as to which clock >> edge samples the PPS on each device. You might need a custom FPGA image to >> solve for your particular configuration, it’s a tricky timing problem. >> (Of course something else also may also be going on….custom >> configuration=custom problems!) >> -Ian >> >> On Jun 18, 2018, at 11:08 AM, Дмитрий Михайличенко via USRP-users < >> usrp-users@lists.ettus.com> wrote: >> >> OK. Now I am trying to synchronize channels on UBX only boards. I am able >> to get them synchronized if I use default master clock rate 200 MHz. >> For my test I use modified UHD driver that allows to set 122.88 MHz >> master clock. It seems that phase sync procedure does not work in that case. >> >> thanks, >> Dmitry >> >> пн, 18 июн. 2018 г. в 18:22, Marcus D. Leech via USRP-users < >> usrp-users@lists.ettus.com>: >> >>> On 06/18/2018 10:57 AM, Дмитрий Михайличенко via USRP-users wrote: >>> >>> Is it important to have PPS signal aligned with reference 10 MHz signal. >>> In my case they come from different sources. >>> >>> thanks, >>> Dmitry? >>> >>> Something to be aware of though is that trying to achieve fine phase >>> synchronization (with predictable phase offset) between two >>> entirely-different synthesizer types is not likely to be all that >>> satisfying. >>> >>> Different types of synthesizers will interpret the re-synch pulse sent >>> by the FPGA in slightly different ways, so achieving very-tight >>> synchronization between different board types is not likely to work. >>> >>> >>> >>> пн, 18 июн. 2018 г. в 17:37, Marcus D. Leech via USRP-users < >>> usrp-users@lists.ettus.com>: >>> >>>> On 06/18/2018 10:28 AM, Дмитрий Михайличенко via USRP-users wrote: >>>> >>>> The frequency is around 600 MHz. I also tried higher frequencies. The >>>> offset is visible on picture attached. >>>> >>>> thanks, >>>> Dmitry >>>> >>>> If you look here: >>>> >>>> https://kb.ettus.com/UBX >>>> >>>> You can see that for frequencies below 1GHz, you have to use a 20MHz >>>> daughterboard clock for UBX to achieve synchronization. >>>> I don't know if SBX will work correctly with a 20MHz daughterboard >>>> clock, so you can't have "mixed" UBX + SBX on the same >>>> X310. >>>> >>>> Also, integer-N tuning can help maintain better phase synchronization >>>> characteristics: >>>> >>>> https://files.ettus.com/manual/structuhd_1_1tune__request__t.html >>>> >>>> >>>> пн, 18 июн. 2018 г. в 14:50, Дмитрий Михайличенко <mdm...@gmail.com>: >>>> >>>>> Hi, >>>>> >>>>> I have a couple of X310 each of them has UBX+SBX cards. The devices >>>>> are synchronized by external 10MHz + PPS signal. But in my test I see >>>>> random phase delay between all channels that varies between test runs. The >>>>> test creates multi usrp device, sets up time and tunes to the same >>>>> frequency using timed command, then it captures some buffers. The same >>>>> external signal is supplied to all antenna ports. Is it expected to have >>>>> random delay between channels? Is there any way to have constant phase >>>>> delay from run to run? >>>>> >>>>> thanks, >>>>> Dmitry >>>>> >>>> >>>> >>>> _______________________________________________ >>>> USRP-users mailing >>>> listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>>> >>>> _______________________________________________ >>>> USRP-users mailing list >>>> USRP-users@lists.ettus.com >>>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>>> >>> >>> >>> _______________________________________________ >>> USRP-users mailing >>> listUSRP-users@lists.ettus.comhttp://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >>> >>> _______________________________________________ >>> USRP-users mailing list >>> USRP-users@lists.ettus.com >>> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >>> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> >> >> _______________________________________________ >> USRP-users mailing list >> USRP-users@lists.ettus.com >> http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com >> > _______________________________________________ > USRP-users mailing list > USRP-users@lists.ettus.com > http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com > > >
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