Hi, I'm trying to add an AXI Uartlite (https://www.xilinx.com/support/documentation/ip_documentation/axi_uartlite/v2_0/pg142-axi-uartlite.pdf) module to the E310 and will be using two GPIO pins for the serial TX/RX. I've added the IP to e310.v, and hooked it up to twp GPIO pins and the AXI Interconnect, and the project seems to build fine. The problem is that there is no block diagram for the E310 FPGA project, so I'm not sure where to assign the base address for the AXI Uartlite. If there were a block diagram, there is a tab where you can assign the address, and then that address is what goes into the device tree. Is there somewhere else I can assign the address? Or is it automatically assigned and I've missed it somewhere? Thanks, Anisha
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