Following up on this, I have an additional question: is there any plan to expose the DC offset and IQ balance API through device3? Currently it appears as though the legacy interface can make use of these functions to manually set IQ balance and DC offset, while device3-based programs (i.e., anything using RFNoC) cannot. Am I correct in this?
Nick On Thu, Jun 28, 2018 at 6:22 PM Nick Foster <bistrom...@gmail.com> wrote: > Hi all, > > I haven't looked at daughterboard calibration in a long time, and picking > it up, it sure looks broken to me. I'm using X310 + WBX on rfnoc-devel as > of March. Let's assume for the moment I'm running a stock FPGA image -- I'm > not, but for testing I replicated the same results on the stock image. > > I ran TX DC offset cal as follows: > uhd_cal_tx_dc_offset --args=addr=192.168.10.2 --freq_start=70e6 > --freq_stop=150e6 --freq_step=1e6 > > And I ran TX IQ imbalance cal as follows: > uhd_cal_tx_iq_balance --args=addr=192.168.10.2 --freq_start=70e6 > --freq_stop=150e6 --freq_step=1e6 > > Both DC offset and IQ imbalance are significantly worse after running > calibration. DC offset is 30dB higher and IQ imbalance is 27dB worse. > > I also tried default parameters in case the frequency step is sensitive to > the TX offset setting, with no change (it actually got somewhat worse...). > > Is there anything I should know about the calibration utilities which > prevents them from being used on relatively recent UHD releases? Did > someone cross up the I and Q channels in the correction registers? > > Nick >
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