On Mon, Aug 6, 2018 at 3:37 AM TIMMEN Koen < koen.tim...@thalesaleniaspace.com> wrote:
> Brian, > > > > I am not sure if I have stated my problem clearly. So I will reformulate: > My HDL module which I have verified using testbenches needs to be > controlled from the UHD API. However, I have trouble doing this. Following > the two examples available from the source directory I connected my blocks > as follows (using uhd:rfnoc::graph::connect(), without creating a streamer): > > > > SIGGEN à DUC à RADIO > > > > However, the USRP device does not transmit any samples. > > > > As I indicated, I am not sure whether or not to generate a stream. Because > I don’t know what it is intended for. Should I for example create a stream > object to manage the sample flow from the SIGGEN to the DUC? Or will it > suffice to use uhd::rfnoc::graph::connect(). Or do I need to use both? > Sorry for the confusion. No, you just need to connect the graph together and the blocks should be stitched together. > > > Then finally, once I have initialized and connected all blocks, how do I > indicate to the radio it can start transmitting samples? The SIGGEN block > generates samples after I write in a certain user register. It then stores > these samples in a FIFO, which should offload the samples to the next block > as soon as this activates ‘tready’. But I’m not sure if this ever happens > or if the ‘tready’ signal might not be linked correctly for example. > You just need to write to the appropriate register. To verify the tready signal in your design, you can use the internal logic analyzer in Vivado and check out what the core internally is doing. > > > Hopefully now I indicated my struggles a bit better, if anything is > unclear please don’t hesitate to let me know. > Yes, it was more clear. Sorry for the confusion. Hopefully this is more clear. Brian >
_______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
