I am not sure what I've done, but all of a sudden I don't seem to be able to
run my testbench. Things are in the "compiling" stage of the testbench when I
get hit with this:
Built simulation snapshot ddc_chain_behav
****** Webtalk v2017.4 (64-bit)
**** SW Build 2086221 on Fri Dec 15 20:54:30 MST 2017
**** IP Build 2085800 on Fri Dec 15 22:25:07 MST 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source
/opt/gnuradio/v3.7.12.0_rfnoc/src/rfnoc-nocblocks/rfnoc/testbenches/noc_block_responder_tb/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/xsim.dir/ddc_chain_behav/webtalk/xsim_webtalk.tcl
-notrace
INFO: [Common 17-186]
'/opt/gnuradio/v3.7.12.0_rfnoc/src/rfnoc-nocblocks/rfnoc/testbenches/noc_block_responder_tb/xsim_proj/xsim_proj.sim/sim_1/behav/xsim/xsim.dir/ddc_chain_behav/webtalk/usage_statistics_ext_xsim.xml'
has been successfully sent to Xilinx on Wed Aug 8 08:40:08 2018. For
additional details about this file, please refer to the WebTalk help file at
/opt/Xilinx/Vivado/2017.4/doc/webtalk_introduction.html.
INFO: [Common 17-206] Exiting Webtalk at Wed Aug 8 08:40:08 2018...
run_program: Time (s): cpu = 00:00:04 ; elapsed = 00:00:05 . Memory (MB): peak
= 1340.074 ; gain = 0.000 ; free physical = 48514 ; free virtual = 292443
INFO: [USF-XSim-69] 'elaborate' step finished in '5' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in
'/opt/gnuradio/v3.7.12.0_rfnoc/src/rfnoc-nocblocks/rfnoc/testbenches/noc_block_responder_tb/xsim_proj/xsim_proj.sim/sim_1/behav/xsim'
INFO: [USF-XSim-98] *** Running xsim
with args "ddc_chain_behav -key {Behavioral:sim_1:Functional:ddc_chain}
-tclbatch {ddc_chain.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.4
Time resolution is 1 ps
source ddc_chain.tcl
## current_wave_config
ERROR : The following component DSP48A1 at instance
ddc_chain.old_hb.small_hb_i.mult.dsp_st.DSP48AST is not supported for
retargeting in this architecture. Please modify your source code to use
supported primitives. The complete list of supported primitives for this
architectures is provided in the 7 Series HDL Libraries Guide available on
www.xilinx.com.
$finish called at time : 0 fs : File
"/wrk/2017.4/nightly/2017_12_15_2086221/data/verilog/src/retarget/DSP48A1.v"
Line 74
INFO: [USF-XSim-96] XSim completed. Design snapshot 'ddc_chain_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000000000us
launch_simulation: Time (s): cpu = 00:00:12 ; elapsed = 00:00:16 . Memory (MB):
peak = 1407.582 ; gain = 112.375 ; free physical = 48509 ; free virtual = 292438
# if [string equal $vivado_mode "batch"] {
# puts "BUILDER: Closing project"
# close_project
# } else {
# puts "BUILDER: In GUI mode. Leaving project open."
# }
BUILDER: Closing project
I didn't update UHD or anything like that, so I can't figure out what I've
done wrong. I assume the DSP48A1 is because I am attempting to use most of the
siggen code in my block. This seemed to be working fine, and then this hit all
of a sudden.
Any thoughts?
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