I wouldn't mind seeing your solution to #2 as well. The messages certainly make things look more ominous than they actually are. --------- Original Message --------- Subject: Re: [USRP-users] Can't find a block controller for key FFT, using default block controller! From: "EJ Kreinar via USRP-users" <usrp-users@lists.ettus.com> Date: 9/24/18 7:51 pm To: "Rich Maes" <r...@idearockets.com> Cc: "USRP-users@lists.ettus.com" <usrp-users@lists.ettus.com>
Hi Rich, This all looks OK to me. 1) the block controller warning just indicates there's no *custom* block controller for a particular block. By default the XML noc block definition will typically populate read/write registers in a default block controller just fine. 2) the errors at the end are expected for the e310, as you have indicated. I've suppressed these myself; perhaps I'll write this up and provide an out of tree fix for those of us who dont want to always see the errors output to console. EJ On Mon, Sep 24, 2018, 5:35 PM Rich Maes via USRP-users <usrp-users@lists.ettus.com> wrote: Re-pining this question On Sep 2, 2018, at 10:48 PM, Rich Maes <r...@idearockets.com> wrote: I am running a cross-compiled UHD environment on a E310. I have a couple warning that appear when I am running my uhd_usrp_probe with a custom FPGA image. The image I have created has 2 FFT's and 2 Windows in it. The warning indicate that the controller blocks cannot be found for the FFT's. Later, at the bottom of the run, I get some errors like the following [ERROR] [UHD] Exception caught in safe-call. I would like to confirm that the lack of a controller for the FFT is a real problem that needs to be resolved. Relative to the exceptions at the end, I have read that although this is an error, it does not prevent running applications http://lists.ettus.com/pipermail/usrp-users_lists.ettus.com/2017-March/051914.html root@ettus-e3xx-sg3:~/localinstall/usr/share/uhd/images# uhd_usrp_probe --args='fpga=usrp_e310_fpga_RFNOC_sg3.bit' [INFO] [UHD] linux; GNU C++ version 4.9.2; Boost_105700; UHD_4.0.0.rfnoc-devel-702-geec24d7b [INFO] [E300] Loading FPGA image: usrp_e310_fpga_RFNOC_sg3.bit... [INFO] [E300] FPGA image loaded [INFO] [E300] Initializing core control (global registers)... [INFO] [E300] Performing register loopback test... [INFO] [E300] Register loopback test passed [INFO] [0/Radio_0] Initializing block control (NOC ID: 0x12AD100000000000) [INFO] [0/Window_0] Initializing block control (NOC ID: 0xD053000000000000) [INFO] [0/Window_1] Initializing block control (NOC ID: 0xD053000000000000) [WARNING] [RFNOC] Can't find a block controller for key FFT, using default block controller! [INFO] [0/FFT_0] Initializing block control (NOC ID: 0xFF70000000000000) [WARNING] [RFNOC] Can't find a block controller for key FFT, using default block controller! [INFO] [0/FFT_1] Initializing block control (NOC ID: 0xFF70000000000000) _____________________________________________________ / | Device: E-Series Device | _____________________________________________________ | / | | Mboard: E3XX SG3 | | product: 30675 | | revision: 7 | | serial: 3150D1D | | mac-addr: 00:80:2f:19:10:70 | | FPGA Version: 255.0 | | FPGA git hash: 1b40696-dirty | | RFNoC capable: Yes | | | | Time sources: none, internal, external | | Clock sources: internal | | Sensors: temp, ref_locked | | _____________________________________________________ | | / | | | RX DSP: 0 | | | | | | Freq range: 0.000 to 0.000 MHz | | _____________________________________________________ | | / | | | RX DSP: 1 | | | | | | Freq range: 0.000 to 0.000 MHz | | _____________________________________________________ | | / | | | RX Dboard: A | | | ID: E310 MIMO XCVR (0x0110) | | | Serial: 314E574 | | | _____________________________________________________ | | | / | | | | RX Frontend: A | | | | Name: FE-RX2 | | | | Antennas: TX/RX, RX2 | | | | Sensors: temp, rssi, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Frontend: B | | | | Name: FE-RX1 | | | | Antennas: TX/RX, RX2 | | | | Sensors: temp, rssi, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 76.0 step 1.0 dB | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | RX Codec: A | | | | Name: E3x0 RX dual ADC | | | | Gain Elements: None | | _____________________________________________________ | | / | | | TX DSP: 0 | | | | | | Freq range: 0.000 to 0.000 MHz | | _____________________________________________________ | | / | | | TX DSP: 1 | | | | | | Freq range: 0.000 to 0.000 MHz | | _____________________________________________________ | | / | | | TX Dboard: A | | | ID: E310 MIMO XCVR (0x0110) | | | Serial: 314E574 | | | _____________________________________________________ | | | / | | | | TX Frontend: A | | | | Name: FE-TX2 | | | | Antennas: TX/RX | | | | Sensors: temp, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Frontend: B | | | | Name: FE-TX1 | | | | Antennas: TX/RX | | | | Sensors: temp, lo_locked | | | | Freq range: 50.000 to 6000.000 MHz | | | | Gain range PGA: 0.0 to 89.8 step 0.2 dB | | | | Bandwidth range: 200000.0 to 56000000.0 step 0.0 Hz | | | | Connection Type: IQ | | | | Uses LO offset: No | | | _____________________________________________________ | | | / | | | | TX Codec: A | | | | Name: E3x0 TX dual DAC | | | | Gain Elements: None | | _____________________________________________________ | | / | | | RFNoC blocks on this device: | | | | | | * Radio_0 | | | * Window_0 | | | * Window_1 | | | * FFT_0 | | | * FFT_1 [INFO] [E300] Loading FPGA image: /home/root/localinstall/usr/share/uhd/images/usrp_e3xx_fpga_idle_sg3.bit... [INFO] [E300] FPGA image loaded [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 [ERROR] [UHD] Exception caught in safe-call. in ctrl_iface_impl<_endianness>::~ctrl_iface_impl() [with uhd::endianness_t _endianness = (uhd::endianness_t)1u] at /home/rich/e300/src/uhd/host/lib/rfnoc/ctrl_iface.cpp:60 this->send_cmd_pkt(0, 0, true); -> AssertionError: (sts >> 7) & 0x1 in typename T::sptr e300_transport::get_buff(double) [with T = uhd::transport::managed_send_buffer; typename T::sptr = boost::intrusive_ptr<uhd::transport::managed_send_buffer>] at /home/rich/e300/src/uhd/host/lib/usrp/e300/e300_fifo_config.cpp:250 root@ettus-e3xx-sg3:~/localinstall/usr/share/uhd/images# _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com _______________________________________________ USRP-users mailing list USRP-users@lists.ettus.com http://lists.ettus.com/mailman/listinfo/usrp-users_lists.ettus.com
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